In conjunction with SC’25, St. Louis, MO, November 17th, 2025

Overview and scope

Heterogeneity is ubiquitous, not only in terms of processing units but also memories and networks. As heterogeneity increases, memory subsystems play an even more important role to attain performance, from their technology to the system architecture to the software management and programming model. While CPU-only compute nodes are becoming rare instances, heterogeneous memory architectures have recently emerged and revolutionized the traditional memory hierarchy. Today’s and upcoming architectures may well comprise multiple memory technologies next to DRAM, accelerators with dedicated memories, or even specific expansion cards hosting memory alone, such as: 3D-stacked memory, high-bandwidth multi-channel RAM, unified/shared memory on accelerators, Compute Express Link (CXL)-based architectures, persistent memory, or MRDIMMs.

As in previous years, the Workshop on Heterogeneous Memory Systems, now rebranded as Heterogeneity and Memory Systems (HMEM), will bring together different research efforts and expertise to the end of integrating different approaches and democratizing the use of resource heterogeneity from a memory perspective, to benefit applications not only in terms of performance, but also energy efficiency and cost trade-offs. The main goal of the workshop is to push the research frontiers forward by exchanging knowledge and debating ideas through featured talks, technical paper presentations, and interactive discussions. Overall, topics of interest include, but are not limited to:

Resource heterogeneity (e.g., accelerators) and memory implications, including memory designs, data layouts, etc.
Data allocation and placement techniques in heterogeneous memory systems
Caching for heterogeneous memory systems
Programming models and tools for complex/heterogeneous memory hierarchies
Software-defined far memories
Disaggregated memory and in-memory computing
Data movement in heterogeneous memory systems
Memory consistency and persistency models
Data structures for heterogeneous memory infrastructures
Abstractions and support for failure-atomicity in persistent memory
Emerging memory architectures and system configurations
AI on heterogeneous memory systems and use of AI for heterogeneous memory systems
Use cases, early experiences and performance evaluations

Submissions

This is a traditional-style workshop without formal proceedings. The authors of accepted submissions will give a talk at the workshop and participate in the closing discussion panel. Additionally, authors will be invited to (optionally) upload their submitted paper (PDF) to be shared on the workshop website. A paper accepted to the HMEM workshop does not preclude its future publication at a major conference.

Submissions must use the ACM proceedings template (for Latex users, version 1.90 (last update April 4, 2023) is the latest template, and please use the “sigconf” option).

We accept two types of submissions.

A first type of submission includes position papers as well as papers that describe completed or early-stage work. Such submissions are limited to 12 pages including references and figures.
Extra pages can be included in a clearly marked appendix (to be read at the discretion of the reviewers). Submitted papers must not include author names (double-blind review).

We also welcome 2-page abstracts that summarize recently accepted/published at top-tier conferences/journals. In this case, the author names and references to the published works should be included in the abstract.

Submit your paper here: https://submissions.supercomputing.org

Important dates

Submission deadline: August 26th, 2025
Notification of acceptance: September 15th, 2025
Workshop: November 17th, 2025

Time Zone: AOE (Anywhere One Earth)

Organization committee

Harald Servat, Intel
João Barreto, INESC-ID, Universidade de Lisboa
Antonio J. Peña, Barcelona Supercomputing Center (BSC)

Program committee

Adrian Jackson, EPCC, UK
Alexandro Baldassin, Universidade Estadual Paulista, Brasil
Gokcen Kestor, PNNL, USA
Dong Li, University of California, Merced, USA
Gulay Yalcin, Abduallah Gul University, Turkey
Ivy Peng, LLNL, USA
Maciej Maciejewski, Huawei, Poland
Marc Jordá, Barcelona Supercomputing Center, Spain
Manolis Marazakis, Foundation for Research and Technology – Hellas (FORTH), GR
Swann Perarnau, Argonne National Laboratory (ANL), University of Chicago, USA
Petar Radojkovic, Barcelona Supercomputing Center, Spain
Tim Dykes, HPE, UK