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IITC 2008 : IEEE International Interconnect Technology Conference


When Jun 1, 2008 - Jun 4, 2008
Where Burlingame, CA, USA
Submission Deadline Jan 29, 2008
Categories    electron devices

Call For Papers

The tenth annual IITC is sponsored by the IEEE Electron Devices Society as a premier conference for interconnect technology. The IITC provides a forum for professionals and researchers in semiconductor processing, advanced materials, equipment development, and interconnect systems to present and discuss exciting new science and technology.


Technical Papers: Contributed papers addressing all aspects of interconnect technology will be rigorously reviewed. Papers will be selected for either oral or poster presentation.

Exhibits/Seminars: New products, processes, analytical methods and materials will be exhibited at the conference on June 4 and 5. Supplier seminars will be held on the 1st and 2nd evenings of the conference. Please contact the Conference Headquarters for details.

Short Course: A one-day short course on leading edge interconnect technology will be offered on Sunday, June 3, 2007.


Deadline: January 29, 2007

Oral presentations will be 20 minutes in length followed by a 5 minute question period. Authors should send only original, unpublished work. Paper submissions that have been previously presented or published will not be accepted. Appropriate company or government clearance must be obtained by the authors before submission. Submitted papers will not be returned to the authors.

Papers must be submitted electronically (SUBMIT PAPER). Do not email or mail hard copies to the conference office. Please read the paper preparation and submission guidelines before preparing your paper. In order for your paper to receive a full review, the following information MUST be entered on the website along with your submission:

* Title of paper
* First author name with complete mailing address, phone, fax and email address
* Names, affiliations, city state or country of additional authors
* Person to whom correspondence should be sent, if other than the first author
* Identification as invited or student paper; and student travel request if applicable

ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT THE OPPORTUNITY FOR FURTHER CHANGE. Papers must be 3 pages in length inclusive of all illustrations, charts and tables. Contact information for each author must be listed on the first page of the paper: name, affiliation, city, state or country. Authors of accepted papers will be notified by March 16, 2007.

Note: Accepted papers may be used for publicity purposes and portions of these papers may be quoted in pre-conference magazine articles and also via the Web. If this is NOT acceptable, authors must indicate this in the cover letter when submitting the paper for review.


Dielectrics: Dielectric materials (low k, high k, ARCs, etc.) and deposition processes (vapor deposition, CVD, spin-on, etc.) for interconnect applications.

CMP/Planarization: Dielectric/Metal CMP processes, equipment and metrology issues. Alternative planarization techniques.

Metallization: Metal deposition processes/equipment (PVD, CVD, ALD, electroplating) and materials characterization with particular emphasis on advanced aluminum and copper metallization.

Process Integration: Multilevel interconnect processes, clustered processes, novel interconnect structures, contact/via integration, metal barrier and materials interface issues, etc.

Process Control/Modelling: CMP, metal/dielectric deposition and etching processes, PVD, CVD, electroplating, etc.

Reliability: Metal electromigration and stress voiding, dielectric integrity and mechanical stability, thermal effects, passivation issues, interconnect reliability prediction/modeling.

Interconnect Systems: Interconnect performance modeling and high frequency characterization, interconnect system integration and advanced packaging concepts (flip-chip, chip-on-chip, MCM, etc.), novel architectures and advanced interconnect concepts (optical, superconductors, etc.).

System-on-a-Chip: Interconnect, design and processing of SOC, embedded memory processing, materials and integration, RF and high frequency passive components, noise and cross-talk issues.

Dry Processing: Dry etching of vias, trenches and damascene structures, dry etching of metal, dry cleaning processes, plasma induced damage, etc.

Alternative Interconnect: Advanced interconnect concepts, optical interconnect, superconductors, nanotechnology-based interconnects, etc.



Deadline: April 13, 2007

A very limited number of papers reporting the latest breakthroughs may be accepted as late news papers. Prospective authors should email ( a pdf file (REMEMBER to "embed all fonts") of the paper. The paper must be two pages in length inclusive of illustrations, charts and tables. Paper format must adhere to the guidelines described in the Author's Kit. Accepted late news papers will be presented orally for 10 minutes followed by a 5 minute question period. Late news papers will be printed in the conference proceedings but will not be included in the advance program. An IEEE copyright form will be required.


For additional information, including Author's Kits, Supplier/Exhibit Information, Registration/Hotel Information, please contact:

IITC c/o Widerkehr & Associates, 16220 South Frederick Avenue, Suite 312 Gaithersburg, MD 20877 USA, Tel. +1-301-527-0900 x104, Fax. +1-301-527-0994, Email:

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