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ISLPED 2024 : ACM/IEEE International Symposium on Low Power Electronics and Design


Conference Series : International Symposium on Low Power Electronics and Design
Link: http://chrome-extension://efaidnbmnnnibpcajpcglclefindmkaj/
When Aug 5, 2024 - Aug 7, 2024
Where Newport Beach, California, USA
Abstract Registration Due Mar 11, 2024
Submission Deadline Mar 18, 2024
Notification Due May 20, 2024
Final Version Due Jun 17, 2024

Call For Papers



Conference date: August 5–7, 2024
Location: Newport Beach, California, USA


Abstract registration: March 11, 2024, at 11:59pm PST
Full paper: March 18, 2024, at 11:59pm PST
Invited Talk, Panel, and Embedded Tutorial Proposals: April 8, 2024
Notification of Paper Acceptance: May 20, 2024
Submission of Camera-Ready Papers: June 17, 2024

The International Symposium on Low Power Electronics and Design (ISLPED) is the premier forum for presentation of innovative research in all aspects of low power electronics and design, ranging from process technologies and analog/digital circuits, simulation and synthesis tools, AI/ML-enhanced EDA/CAD, system-level design, and optimization, to system software and applications. Specific topics include, but are not limited to, the following three main tracks and sub-areas:

1. Technology, Circuits, and Architecture
1.1. Technologies
Low-power technologies for device, interconnect, logic, memory, 2.5/3D, cooling, harvesting, sensors, optical, printable, biomedical, battery, and alternative energy storage devices and technology enablers for non-Boolean and quantum/quantum-inspired compute models.

1.2. Circuits
Low-power circuits for logic, memory, reliability, yield, clocking, resiliency; low-power analog/mixed-signal circuits for wireless, RF, MEMS, ADC/DAC, I/O, PLLs/DLLs, DC-DC converters; energy-efficient circuits for emerging applications (e.g., neuromorphic, biomedical, in-vitro sensing, autonomous); circuits using emerging technologies; cryogenic circuits. DTCO for low power; combinatorial optimizers (Ising machine).

1.3. Logic and Architecture
Low-power logic and microarchitecture for SoC designs, processor cores (compute, graphics, and other special purpose cores), cache, memory, arithmetic/signal processing, cryptography, variability, asynchronous design, and non-conventional computing. System technology co-optimization (STCO) for low power.

2. EDA, Systems, and Software
2.1. CAD Tools and Methodologies
CAD tools, methodologies, and AI/ML-based approaches for low-power and thermal-aware design (analog/digital). AI/ML for acceleration of circuit simulation and IP block design convergence. Power estimation, optimization, reliability, and variation impact on power optimization at all levels of design abstraction: physical, circuit, gate, register transfer, behavior, and algorithm.

2.2. Systems and Platforms
Low-power, power-aware, and thermal-aware system design including data centers, SoCs, embedded systems, Internet-of-Things (IoT), wearable computing, body-area networks, wireless sensor networks, and system-level power implications due to reliability and variability. Applications of AI/ML-based solutions and brain-inspired computing to power-aware system and platform design.

2.3. Software and Applications
Energy-efficient, energy/thermal-aware software and application design, including scheduling and management, power optimization through HW/SW co-design, and emerging low-power AI/ML applications.

3. Crosscutting Topics
3.1. AI/ML Hardware
Low-power AI/ML HW techniques including approximations, application driven optimizations, in-memory/near-memory/energy-efficient accelerations, and neuromorphic computing; energy-efficient HW and systems for generative AI applications (LLMs, diffusion models); energy-efficient AI/ML HW using emerging technologies (including quantum computing); analog/mixed-signal computing.

3.2. Hardware and System Security
Low-power hardware security primitives (PUF, TRNG, cryptographic/post-quantum cryptographic accelerators), nano-electronics security, supply chain security, IoT security and AI/ML security; confidential computing; energy-efficient approaches to system security.

4. Industrial Design Track
ISLPED’24 solicits papers for an “Industrial Design” track to reinforce interaction between the academic research community and industry. Industrial Design track papers have the same submission deadline as regular papers and should focus on similar topics but are expected to provide a complementary perspective to academic research by focusing on challenges, solutions, and lessons learnt while implementing industrial-scale designs.

Submissions (not published/accepted/under review by another journal, conference, symposium, or workshop) should be full-length papers of up to 6 pages (PDF format, double-column, US letter size, using the ACM proceedings “sigconf” template, available at ( including all illustrations, tables, references, and an abstract of no more than 250 words. Submissions must be anonymous. Submissions failing above requirements will be automatically rejected. Accepted papers will be submitted to the IEEE Xplore Digital Library and the ACM Digital Library. ISLPED’24 will present three Best Paper Awards based on the ratings of reviewers and a panel of judges.

ISLPED also features a Low Power Design Contest with live demonstrations and awards. Submissions are due on May 13, 2024. More details will soon be available on the conference web page.
There will be several invited talks by industry and academic thought leaders on key issues in low power electronics and design. The Symposium may also include embedded tutorials to provide attendees with the necessary background to follow recent research results, as well as panel discussions on future directions in low power electronics and design. Proposals for invited talks, embedded tutorials, and panels should be sent by email to the ISLPED’24 Technical Program Co-Chairs, Kapil Dev ( and Jerald Yoo ( by the deadline listed above.
Participants interested in exhibiting at the Symposium should contact the General Chair by April 29, 2024.

Organizing Committee and Symposium Officers:

General Chair: Pascal Meinerzhagen, Intel

Program Co-Chairs: Kapil Dev, Nvidia / Jerald Yoo, NUS /

Local Arrangements Chair: Mehdi Kamal, USC

Treasurer: Mehdi Kamal, USC

Publications Chair: Younghyun Kim, Wisconsin Univ.

Web/Registration Co-Chairs: Meron Demissie, UMich / Ganapati Bhat, WSU /

Publicity Co-Chairs: Semeen Rehman, TU Wien / Jaeha Kung, Korea Univ / Linghao Song, UCLA / /

Design Contest Co-Chairs: Rajesh Kedia, IITH / Payam Heydari, UCI /

Industry Liaison Co-Chairs: Adam Teman, BIU / Amlan Ganguly, RIT /

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