DASIP 2024 Call for Papers


The Workshop on Design and Architectures for Signal and Image Processing (DASIP) provides an inspiring international forum for the latest innovations and developments in the field of leading signal, image and video processing and machine learning in custom embedded, edge and cloud computing architectures and systems. The workshop program will include keynote speeches and contributed paper sessions. The 17th edition will be held in conjunction with the 19th HiPEAC Conference in Munich, Germany, January 17-19, 2024.


SUBMISSION GUIDELINES

Authors should prepare their full papers (up to 12 pages, single-column Springer format), and/or short papers (up to 6 pages, single-column Springer format, intended for work-in-progress with promising results and/or students at the early stages of their research), using the Springer LNCS template.

Submitted papers are required to describe original unpublished work and must not be under consideration for publication elsewhere. Submissions must be fully anonymous, but authors should not hide previous work, instead, they need to make self-references in the third person. More details on submission requirements, templates and submission instructions are provided on the DASIP website:

https://dasipws.github.io/

Each submission will receive at least three independent double blind reviews from the members of our scientific committee. Authors will be encouraged to take the reviewers’ comments into account when they prepare the final versions of their papers and present the research during the workshop prior to its publication. Paper and keynote presentation slides and tutorial documents will be made available to workshop attendees after the workshop (subject to confidentiality issues).


IMPORTANT DATES (ALL 23:59 A.O.E)

Abstract submission deadline: October 6th, 2023
Paper submission deadline: October 13th, 2023
Notification of acceptance: November 24th, 2023
Camera ready papers: December 1st, 2023
Workshop : January 17-19, 2024






LIST OF TOPICS

Prospective authors are invited to submit manuscripts on topics including, but not limited to:

=) Custom embedded, edge and cloud architectures and systems:
- Machine learning and deep learning architectures for inference and training
- Systems for autonomous vehicles : cars, drones, ships and space applications
- Image processing and compression architectures
- Smart cameras, security systems, behaviour recognition
- Edge and cloud processing : special routing, configurable co-processors and low
energy considerations
- Real-time cryptography, secure computing, financial and personal data processing
- Computer arithmetic, approximate computing, probabilistic computing,
nanocomputing, bio-inspired computing
- Biological data collection and analysis, bioinformatics
- Personal digital assistants, natural language processing, wearable computing and
implantable devices
- Global navigation satellite and inertial navigation systems

=) Design Methods and Tools:
- Design verification and fault tolerance
- Embedded system security and security validation
- System-level design and hardware/software co-design
- High-level synthesis, logic synthesis, communication synthesis
- Embedded real-time systems and real-time operating systems
- Rapid system prototyping, performance analysis and estimation
- Formal models, transformations, algorithm transformations and metrics

=) Development Platforms, Architectures and Technologies:
- Embedded platforms for multimedia and telecommunication
- Many-core and multi-processor systems, SoCs, and NoCs
- Reconfigurable ASIPs, FPGAs, and dynamically reconfigurable systems
- Memory system and cache management
- Asynchronous (self-timed) circuits and analog and mixed-signal circuits



COMMITTEES

=) Steering Committee
Joao M. P. Cardoso, University of Porto, Porto, Portugal
Miguel Chavarrías, Universidad Politécnica de Madrid, Madrid, Spain
Jean-Pierre David, Ecole Polytechnique de Montreal, Montreal, Canada
Karol Desnos, INSA Rennes – IETR laboratory, Rennes, France
Sebastien Pillement, University of Nantes – IETR, Nantes, France
Andrea Pinna, Sorbonne University, Paris, France
Diana Goehringer, TU Dresden, Dresden, Germany
Marek Gorgoń, AGH University of Science and Technology, Kraków, Poland
Michael Huebner, Brandenburg University of Technology, Cottbus-Senftenberg, Germany
Tomasz Kryjak, AGH University of Science and Technology, Kraków, Poland
Pierre Langlois, Ecole Polytechnique de Montreal, Montreal, Canada
Paolo Meloni, University of Cagliari, Cagliari, Italy
Sergio Petruz, TU Dresden, Dresden, Germany
Alfonso Rodríguez, Universidad Politécnica de Madrid, Madrid, Spain

=) Organizing committee

Tiago Miguel Braga da Silva Dias, Instituto Superior de Engenharia de Lisboa, Portugal
Paola Busia, University of Cagliari, Italy

VENUE

The Workshop on Design and Architectures for Signal and Image Processing will be held in conjunction with the 19th HiPEAC Conference in Munich, Germany, January 17-19, 2024.

CONTACT

All questions about the workshop and submissions should be emailed to Tiago M. Dias (tiago.dias@isel.pt) or Paola Busia (paola.busia@unica.it).