posted by user: mesham || 1791 views || tracked by 3 users: [display]

RISC-V HPC 2023 : First International workshop on RISC-V for HPC

FacebookTwitterLinkedInGoogle

Link: https://riscv.epcc.ed.ac.uk/community/isc23-workshop/
 
When May 25, 2023 - May 25, 2023
Where Hamburg
Submission Deadline Mar 31, 2023
Notification Due Apr 10, 2023
Final Version Due May 1, 2023
Categories    RISC-V   high performance computing   scientific software   novel hardware
 

Call For Papers

================================================================
CALL FOR PAPERS

First International workshop on RISC-V for HPC (RISC-V HPC)

In conjunction with ISC23

https://riscv.epcc.ed.ac.uk/community/isc23-workshop/
=================================================================

RISC-V is an open standard Instruction Set Architecture (ISA) which enables the royalty free development of CPUs and a common software ecosystem to be shared across them. Following this community driven ISA standard, a very diverse set of CPUs have been, and continue to be, developed which are suited to a range of workloads. Whilst RISC-V has become very popular already in some fields, and in 2022 the ten billionth RISC-V core was shipped, to date it has yet to gain traction in HPC.

The goal of this workshop is to continue building the community of RISC-V in HPC, sharing the benefits of this technology with domain scientists, tool developers, and supercomputer operators. There are numerous potential advantages that RISC-V can provide to HPC and, assuming the significant rate of growth of this technology to date continues, as we progress further into the decade it is highly likely that RISC-V will become more relevant and widespread for HPC workloads. Furthermore, recent advances in RISC-V make it a more realistic proposition for HPC workloads than ever before. An example of this is vectorisation extension which provides important performance advantages for HPC workloads but was only standardised in early 2022, and-so we are only now seeing mature CPUs that fully implement this.

The open and standardised nature of RISC-V means that the large, and growing community, can be involved in shaping the standard and tooling. This is important from two perspectives, firstly it is our opportunity in the HPC community to help shape the future of RISC-V to ensure that it is suitable for the next generation of supercomputers. Secondly, whilst there are a wide variety of RISC-V CPUs currently available, the standard nature of the tooling means that very often the same software ecosystem comprising the compiler, operating system, and libraries will run across these whilst requiring few changes.

This workshop aims to bring together those already looking to popularise RISC-V in the field of HPC with the supercomputing community at-large. By sharing benefits of the architecture, success stories, and techniques we hope to further popularise the technology and increase involvement by the community.

Call for papers and workshop topics
-----------------------------------

We invite submissions of high-quality, original research results and works-in-progress on RISC-V with a general connection to HPC. Topics of interest for this workshop include (but are not limited to):

* Example use-cases and case-studies that use RISC-V
* Lessons learnt from leveraging RISC-V in HPC
* Industry papers exploring the use of RISC-V
* The porting of codes to RISC-V
* Novel hardware and accelerators built upon RISC-V
* Tools and techniques to aid in the use of RISC-V for HPC
* Developments in HPC libraries to port them to RISC-V
* Enhancements to RISC-V to make the architecture more suited for HPC
* Compiler and runtime support for RISC-V
* The RISC-V ecosystem
* Future gazing how RISC-V might evolve the HPC community
* And anything else related to RISC-V and HPC!

Paper submission details
------------------------

Authors are invited to submit unpublished, original work. Accepted papers will appear in the ISC post-conference workshop proceedings in the Springer Lecture Notes in Computer Science (LNCS) series and submitted versions available online for the workshop. Submissions are of original work between 6 and 12 pages (the page count does not include references) are welcomed on work-in-progress, position papers, or mature work. All papers should be submitted via EasyChair (https://easychair.org/conferences/?conf=riscvhpc23)

All papers should be formatted Springer single column LNCS style, with formatting information and template (https://www.springer.com/gp/computer-science/lncs/conference-proceedings-guidelines)

Organising committee
--------------------

* Nick Brown (EPCC at the University of Edinburgh)
* John Davis (Barcelona Supercomputing Centre)
* John Leidel (Tactical Computing Labs)
* Andy Gothard (Siemens)
* Michael Wong (Codeplay)

Related Resources

RISC-V HPC 2024   RISC-V for HPC workshop at SC24
ISC 2025   ISC High Performance 2025
RISC-V PPAM 2024   First PPAM Workshop on RISC-V
GPGPU 2025   General Purpose Processing on Graphics Processing Units
RISC-V HPC 2024   Fourth International workshop on RISC-V for HPC
ICCIA--EI 2025   2025 10th International Conference on Computational Intelligence and Applications (ICCIA 2025)
RISCV-HPCAsia 2024   Third International workshop on RISC-V for HPC
HP3C 2025   2025 9th International Conference on High Performance Compilation, Computing and Communications (HP3C 2025)
HPDC- 2025   ACM International Symposium on High-Performance Parallel and Distributed Computing (HPDC) 2025: Call for Papers
ACMLC--EI 2025   2025 7th Asia Conference on Machine Learning and Computing (ACMLC 2025)