General Chair: Dan Gajski, University of California, Irvine
Co-Chair & Organization: Adam Morawiec, ECSI
Program Co-Chairs: Philippe Coussy, Lab-STICC, Université de Bretagne Sud and Sandeep K. Shukla, Virginia Tech University

Conference Descrption

The ever increasing need for enhanced productivity in designing highly complex electronic systems drives the evolution of design methods beyond the traditional approaches. Virtual prototyping, design space exploration and system synthesis with the goal of optimized and functionally correct product implementation are needed for designing both HW and SW parts.

The system design teams expect newer and more efficient methods and tools supporting better management of the design complexity and reduction of the design cycle time all together, breaking the trend to compromise on the evaluation of various design implementation options. Designing at higher levels of abstraction is a viable way to better cope with the system design complexity, to verify earlier in the design process and to increase code reuse.

The Electronic System Level Synthesis Conference ESLsyn focuses on automated system design methods that enable efficient modelling of systems to provide the capability to synthesize HW platforms and embedded software with particular aspects related to synthesis.

Target Audience

This conference will provide an overview of existing and emerging solutions provided by both industrial partners (EDA companies) and research institutions in the domain of ESL synthesis. It will give an outline of synthesis methods and tools available currently in the market and discuss their applicability, performance, strengths and user experiences. Finally, the event will create a discussion platform for experience exchange between providers of synthesis technology and industry users, but also will be a forum to discuss scientific concepts and paradigms for the future evolution of synthesis methods.

Topics

Cyber-Physical System/System/Platform: model-driven synthesis, models of computation, virtual prototyping, design space exploration, design methodologies, architectures, co-design, interface synthesis, partitioning, performance analysis, optimization, modeling refinement, transformation, generation, languages, formal specification and verification methods, virtualization, target platforms: ASIC, FPGA, GPU, many- & multi-core, SOC platforms, HW accelerators, …

High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis for HW Design: hierarchical synthesis, algorithmic transformations, loop transformations, scheduling & binding techniques, correctness, formal verification, reliability, incremental synthesis, control-oriented synthesis, low-power synthesis, performance-driven synthesis, target-specific synthesis, multiple clock design, input languages & subsets, internal representation, interaction with low-level synthesis, certification, trade-off analysis, …

Embedded Software Synthesis: programming models (including multi-core, GPU programming models), correct-by-construction software synthesis, intermediate representations, scheduling techniques, binding, communication and synchronization protocols, middleware/hardware-dependent software, performance analysis and optimization, domain-specific languages and methods (AADL etc.), concurrent program synthesis, compilers for multi-/many- cores, time triggered vs. event triggered models, synchronous programming models, formal methods for embedded software design and verification, …

The above list is not an exhaustive list of topics addressed by ESLsyn; contributions related to ESLsyn problems in general not listed here are highly welcome. Submissions may be theoretical scientific papers, research in progress, case studies, tool use cases and best practice, as well as industry experiences.

Program Committee
Felice Balarin, Cadence Design Systems, USA
Shuvra Bhattacharyya, University of Maryland, USA
Thomas Bollaert, Mentor Graphics, France
Jens Brandt, University of Kaiserslautern, Germany
Forest Brewer, University of California, Santa Barbara, USA
Benjamin Carrion-Schafer, NEC Corporation, Japan
Jason Cong, University of California, Los Angeles, USA
Philippe Coussy, Lab-STICC, Université de Bretagne Sud, France
Steven Derrien, IRISA, France
Robert De Simone, INRIA, France
Mamoun Filali-Amine, IRIT, France
Daniel Gajski, University of California, Irvine, USA
Thierry Gautier, IRISA, France
Abdoulaye Gamatié, LIFL, France
Kim Grüttner, OFFIS, Germany
Yuko Hara-Azumi, Ritsumeikan University, Japan
Christian Haubelt, University of Erlangen-Nürnberg, Germany
Lech Jozwiak, TU Eindhoven, Netherland
Niraj K. Jha, Princeton University, USA
Ryan Kastner, University of California, San Diego, USA
Luciano Lavagno, Politecnico di Torino, Italy
Wayne Luk, Imperial College London, UK
Frédéric Mallet, INRIA, France
Michael McNamara, Cadence Design Systems, USA
Michael Meredith, Forte Design Systems, USA
Maria Carmen Molina, Universidad Complutense de Madrid, Spain
Adam Morawiec, ECSI, France
Stephen Neuendorffer, Xilinx, USA
Bernhard Niemann, Fraunhofer, Germany
Rishiyur Nikhil, Bluespec, USA
Marc Pantel, IRIT, Université de Toulouse, France
Hiren Patel, University of Waterloo, Canada
Dumitru Potop-Butucaru , INRIA, France
Tanguy Risset, CITI - INSA Lyon, France
Eric Rutten, INRIA, France
John Sanguinetti, Forte Design Systems, USA
Sandeep Shukla, Virginia Tech University, USA
Johannes Stahl, Synopsys
Martin Strecker, IRIT, France
David Thomas, Imperial College London, UK
Hiroyuki Tomiyama, Ritsumeikan University, Japan
Eugenio Villar, University of Cantabria, Spain
Kazutoshi Wakabayashi, NEC Corporation, Japan
Hiroaki Yoshida, University of Tokyo, Japan

Submission Requirements
Authors should submit their full papers (up to 6 pages, double-column IEEE format) in PDF through the web based submission system. Submitted papers should be anonymous, are required to describe original unpublished work and must not be under consideration for publication elsewhere. The conference proceedings will be published in electronic form with the ISSN number and made available in the ECSI Resource Center. Full submission requirements, templates and submission page link can be found at www.ecsi.org/eslsyn.

Important Dates
Paper submission deadline: April 1, 2011 April 14, 2011 (extended)
Notification of acceptance: April 28, 2011
Camera ready papers: May 16, 2011

Demonstrations & Sponsorship
Demonstration of tools will be possible at the conference for ECSI Members and ESLsyn Conference Sponsors. They will benefit from:
- Access to a demonstration booth composed of a poster stand and a table with power plug connection
- Access to the Workshop Registration Lists
- Publicity opportunities
- Reduced Registration Rates
Find out more about Membership benefits and Sponsorship opportunities at www.ecsi.org/eslsyn!

ESLsyn Secretariat
Electronic Chips & Systems design Initiative (ECSI)
Parc Equation – 2, avenue de Vignate - 38610 Gières, France
office@ecsi.org, eslsyn2011@ecsi.org
Ph: +33 4 76 63 49 34, Fax: +33 9 58 08 24 13