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SELSE 2022 : Silicon Errors in Logic - System Effects


When May 19, 2022 - May 20, 2022
Where Virtual
Abstract Registration Due Jan 28, 2022
Submission Deadline Feb 4, 2022
Notification Due Mar 4, 2022
Final Version Due Mar 18, 2022
Categories    electronics   reliability   safety   system-level error management

Call For Papers

The growing complexity and shrinking geometries of modern semiconductor technologies are making high-density, low-voltage devices increasingly susceptible to the influences of electrical noise, process variation, manufacturing defects, transistor aging, and the effects of natural radiation. The system-level impact of these errors can be far-reaching, both in safety-critical aerospace and automotive applications and for large-scale distributed computing. Rapid market evolution and the increase in complexity of electronic devices call for new methodologies to characterize, understand, and improve the reliability of current and future COTS products.
The SELSE workshop provides a unique forum for discussion of current research and practice in error detection, root-cause analysis, and mitigation in computing systems. SELSE solicits papers that address the effects of errors from a variety of hardware, software, and operational perspectives: diagnostic, computational, architectural, logical, circuit-level, and semiconductor processes. Case studies in real-world contexts are also welcome.
We are happy to announce that the best papers presented at SELSE will be selected for inclusion in the “Best of SELSE” session at IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), 2022. These papers will be selected based on the importance of the topic, technical contributions, quality of results, and authors’ agreement to travel to present at DSN in Baltimore, Maryland, USA, on June 27-30, 2022.

Key areas of interest include (but are not limited to):
- Error causes, rates and trends in current and emerging technologies, including experimental failure data and characterization of deployed systems.
- New error detection, analysis, and mitigation techniques and robust software frameworks for resilient system design.
- Improvements in manufacturing and field testing of complex digital systems
- New approaches to the robustness verification of complex hardware and software platforms
- Case studies analyzing the overhead, effectiveness, and design complexity of error diagnosis and mitigation techniques.
- Resilience characterization and strategies for machine learning applications.
- Resilience in new architectures, for example accelerator-rich systems and inexact/approximate computing.
- The design of resilient systems for space exploration.
- The interplay between system security issues and reliability.
- Modeling and tolerating errors in quantum computing: new designs and algorithms to outlive the NISQ era.

Submission Guidelines
Additional information and guidelines for submission are available at Submissions and final papers should be PDF files following the IEEE two-column transactions format. The allowed page limit is fixed to six; the bibliography does not count towards the page limit. Papers are not published through IEEE/ACM nor archived in the digital libraries – however, they are distributed to the workshop attendees.

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