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STEADINESS 2022 : System Engineering and Dependability in Cyber-Physical Systems


When Jun 22, 2022 - Jun 22, 2022
Where Budapest, Hungary
Submission Deadline Mar 31, 2022
Notification Due Apr 18, 2022
Final Version Due May 9, 2022
Categories    verification and validation   languages and compilers   system modelling   parallel computing

Call For Papers

** STEADINESS - System Engineering and Dependability in Cyber-Physical Systems **

** STEADINESS @ HiPEAC 2022 **

This workshop is part of a three day segment in HiPEAC 2022 ( with spotlights
on bridging between contributing communities of Cyber-Physical Systems. Comprising ENHANCE, FORECAST & STEADINESS,
the Segment overview is presented in the programs tab.

STEADINESS encourages participation from system level communities including system modelling, validation and verification and the product lifecycle. Product-side and market influencers, such as from product-lines and policy making are also invited to participate.


The complexity of Cyber-Physical Systems (CPS) has significantly increased. Originally executed on small microcontrollers with few interactions among them, current CPS implement complex functionalities that can benefit from the parallel capabilities of advanced heterogeneous processor architectures featuring accelerator devices, such as GPUs or FPGAs.

Unfortunately, these high-performance requirements are challenging the development processes of CPSs. This is largely due to the fact that CPS rely on model-driven engineering (MDE) techniques, like Domain Specific Modelling Languages (DSMLs),
to preserve the dependability , composability and extensibility properties of the system. MDE methodologies, in turn, lack the necessary features to express the parallelism inherent in the software and the hardware systems. In this context, parallel
programming models (PPMs) (e.g., OpenMP, CUDA) commonly used in the HPC domain, are a fundamental brick to leverage the potential of these architectures, and so cope with the performance requirements of current and future cyber-physical system functionalities.

Overall, the use of complex processor architectures to cope performance requirements of CPS presents two main research challenges in the life cycle of CPS: First, PPMs are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPS and the parallel programming models supported by novel and future embedded platforms. Second, the cyber-physical interactions impose dependability requirements not supported by PPMs.

This workshop seeks innovative contributions in the area of system engineering of CPS with HPC requirements, targeting highly parallel and heterogeneous computing platforms. In particular, papers covering the following topics (but not limited to) are welcome:

* Languages and Compilers for CPS development with parallel and heterogeneous computing support
- Extensions for parallel programming models and languages from syntax, semantic and implementation perspectives, to adapt
parallel frameworks to better express the dependability of CPS.
- Compiler methods to optimise the development and execution of CPS.
* Methodologies, techniques and tools for the V&V of functional and non-functional system properties
- New dependability assessment techniques for complex systems based on analysis, testing or simulation.
- Early dependability assessment methodologies at different abstraction levels (software, microarchitecture, and physical design).
- Timing verification tools and techniques to ease the timing V&V of applications executed in multicore and heterogeneous computing
platforms, statistical and probabilistic approaches for timing analysis, and artificial intelligence techniques for timing bounds
- Static and/or dynamic V&V approaches based on formal methods (e.g., automated or automated theorem proving, model checking,
runtime verification, etc.)
- Combination/marriage of V&V techniques for improved assessment of complex CPS systems
* Dependable parallel runtimes
- Mechanisms towards the dependability of parallel runtimes for CPS frameworks.
- Profiling/tracing and online monitoring tools for an enhanced CPS lifecycle targeting parallel and heterogeneous execution.
* System modeling
- Domain Specific Modelling Languages from different industrial domains, targeting CPS with HPC requirements with focus
on preserving the dependability of the system
- Optimized software synthesis methods, with special interest on those targeting parallel and heterogeneous execution.


- A 2 page extended abstract or a 4-page work in progress papers are invited. A work in progress must include some initial
results. Use the instructions at for preparing your paper. You can find LaTeX templates for
arxiv at
- In the submission system, under the “Topics” option, please select only 1 option, Select STEADINESS to submit to this workshop.
- Please submit your papers at
- The 2 page papers will be only for presentation at the workshop and 4-page accepted papers will also be published as an indexed
proceedings on arxiv.


- Submission date : March 31
- Review dates: April 01 - 15
- Confirmation date : April 18
- Final version date : May 9

** AGENDA **

10.00 Welcome, key note and general discussion on CPS.
11.00 Refreshments
11.30 System Engineering technologies bridging to dependability.
12.00 Lunch
13.00 Model-driven technology applications such as the Automotive Domain
14.30 Refreshments
15.00 Paper & Projects presentations


- Session chaired by: Eduardo Quiñones (BSC)
- Papers review led by: Luis Miguel Pinho (ISEP)


This workshop is supported by the AMPERE and VALU3S projects:
- The AMPERE project ( has received funding from the European Union’s Horizon 2020 research and innovation programme under grant agreement no.: 871669.
- The VALU3S project ( has receibed funding from the ECSEL Joint Undertaking (JU)under grant agreement No 876852. The JU receives support from the European Union’s Horizon 2020 research and innovation programme and Austria, Czech Republic, Germany, Ireland, Italy, Portugal, Spain, Sweden, Turkey.

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