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SLIP 2011 : System Level Interconnect Prediction 2011


Conference Series : System-Level Interconnect Prediction
When Jun 5, 2011 - Jun 5, 2011
Where San Diego, CA
Abstract Registration Due Mar 4, 2011
Submission Deadline Mar 11, 2011
Notification Due Apr 5, 2011
Final Version Due Apr 20, 2011

Call For Papers

The 2011 System Level Interconnect Prediction (SLIP) workshop will be co-located with the 48th IEEE/ACM Design Automation Conference on June 5, 2011 at the Convention Center, San Diego, CA. The general technical scope of the workshop is the design, analysis and prediction of intercommunication fabrics in electronic systems. The organizing committee invites original contributions to the workshop. These contributions include papers, tutorials, panels, and special sessions. Regular papers will be double blind reviewed. We accept papers based on novelty and contributions.
Representative technical topics include, but are not limited to:
1. Interconnect prediction at various IC design stages
2. Interconnect design challenges and system-level NoC design
3. Design and analysis of power and clock networks
4. Interconnect architecture of structural designs and FPGAs
5. Interconnect fabrics of many-core architectures
6. Design-for-manufacturing (DFM) techniques for interconnects.
7. High speed PCB interconnect design
8. Design and analysis of chip-package interfaces
9. Interconnect topologies of multiprocessor systems
10. Interconnect design and prediction of through-silicon vias (TSV) in 3D ICs
11. Emerging interconnect technologies, e.g., RF interconnects, photonic
networks, carbon-based interconnects, etc.
12. Synergies between chip intercommunication networks and networks arising in
other contexts such as social networks, system biology.

Authors are invited to electronically submit papers of up to 8 pages in IEEE proceedings format by following the instructions at
The proceedings of SLIP 2011 will be published by IEEE Press.

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