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CASES 2021 : International Conference on Compilers, Architectures, and Synthesis for Embedded Systems


Conference Series : Compilers, Architecture, and Synthesis for Embedded Systems
When Oct 10, 2021 - Oct 15, 2021
Where Virtual Conference
Abstract Registration Due Apr 2, 2021
Submission Deadline Apr 9, 2021
Notification Due Jul 5, 2021
Categories    embedded systems   compilers   computer architecture   accelerators

Call For Papers

CASES 2021
Call for Papers
International Conference on
Compilers, Architectures, and Synthesis for Embedded Systems
October 10 – October 15, 2021, Virtual Conference

CASES is a premier forum where researchers, developers and practitioners
exchange information on the latest advances in compilers and architectures
for high-performance, low-power, and domain-specific embedded systems.
The conference has a long tradition of showcasing leading edge research
in embedded architectures for processor, memory, interconnect, and
storage, as well as related compiler techniques targeting performance,
power, security, reliability, predictability issues for both traditional
and emerging application domains. We also invite innovative papers
addressing design, synthesis & optimization challenges in heterogeneous,
accelerator-rich architectures.

Journal-Track Submissions
- Abstracts: April 2, 2021
- Full Papers: April 9, 2021 (firm)

Work-in-Progress Submissions
- June 4, 2021 (firm)

Notification of Acceptance
- July 5, 2021 (both tracks)

Topics of Interests / Tracks
Compilers for Embedded Systems: Compilation for power and performance;
Compiler support for CPU, GPU, reconfigurable computing, heterogeneous
and domain-specific multi-core SoC; Compilation for memory, storage, and
on-chip communications.

Processor Architectures: Embedded and mobile processor micro-architecture,
Multi- and many-core processors, GPU architectures, Reconfigurable
computing including FPGAs and CGRAs, Application-Specific processor
design, 3D-stacked architectures; Power- and energy-efficient

Memory and Storage: Memory system architecture; Non-volatile and other
emerging memory technologies; Scratchpad memory, caches and compiler-
controlled memories; storage organization including flash storage.

On-chip communication and I/O: Networks-on-chip architectures and design
methodologies; on-chip communication synthesis, analysis, and
optimization; I/O management in embedded systems.

Accelerators: Synthesis, optimization, and design-space exploration of
high-performance, low-power accelerators; Novel design paradigms and
compilers for accelerators including approximate computing, machine
learning and big-data analytics.

Security, Reliability, and Predictability: Secure architectures, hardware
security, and compilation for software security; Architecture and
compiler techniques for reliability and aging; Modeling, design,
analysis, and optimization for timing and predictability; Validation,
verification, testing & debugging of embedded software.

AI Hardware and ML Applications: Architectures, accelerators, and compilers
for artificial intelligence hardware; Applications of machine learning
algorithm and techniques to embedded systems; Neuromorphic & cognitive
computing, data analytics.

Emerging Applications: Biologically inspired computing; Flexible, stretchable,
and flexible hybrid electronics (FHE); Augmented and virtual reality;
Bioinformatics, and emerging topics on embedded systems.

Journal-Integrated Publication Model
CASES 2021 has a dual publication model with two tracks: Journal track
papers will be published in the ACM Transactions on Embedded Computing
Systems (TECS) and Work-in-Progress track papers will be published in
the ESWEEK Proceedings. See details at

CASES Program Chairs:
Umit Y. Ogras, University of Wisconsin-Madison, USA
Preeti Ranjan Panda, IIT Delhi, IN

ESWEEK General Chairs:
Andreas Gerstlauer, University of Texas at Austin, USA
Aviral Shrivastava, Arizona State University, USA

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