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CASS 2011 : Workshop on Communication Architecture for Scalable Systems


When May 16, 2011 - May 16, 2011
Where Anchorage, Alaska, USA
Submission Deadline Jan 3, 2011
Notification Due Feb 8, 2011
Final Version Due Feb 21, 2011
Categories    computer architecture   distributed computing   interconnection networks

Call For Papers

Call for papers

The 1st Workshop on Communication Architecture for Scalable Systems: CASS 2011 - Anchorage, Alaska, USA, 16 May 2011 -

To be held in conjunction with the International Parallel and Distributed Symposium (IPDPS 2011). CASS represents the evolution of the successful series of CAC workshops held over the past ten years.

- ------------------------------------------------------------ -
- An special issue of Elsevier’s Journal of Parallel and -
- Distributed Processing (JPDC) will be linked with the -
- workshop. Accepted papers will be invited for an -
- extended version -
- ------------------------------------------------------------ -


High-speed communication is critical to all parts of an HPC system. On-chip networks for emerging many-core processors; point-to-point interconnects, which have replaced the system bus for intra-node communication; and system-wide networks, which form the backbone of any large-scale parallel system, all contribute to the construction of the world’s fastest computers. Numerous research groups in academia, industry, and government are currently investigating the issues involved in improving the speed, reliability, power consumption, and other characteristics of communication subsystems and seeking new ways to advance the state of the art in cluster communication.

The goal of this workshop is to bring together researchers working on improving communication at every level of the network hierarchy (on-chip, intra-node, and cross-cluster), thereby enabling the sharing and adaptation of ideas from what have traditionally been separate communities.

All researchers and practitioners working in the area of communication architectures for scalable systems are encouraged to submit a paper to the workshop.

Topics of Interest

Topics of interest for the workshop include but are not limited to the following:
· Hardware and software issues related to router/switch:
- Organization, flow control, collective communication, congestion control, routing and deadlock handling, network topology, load balancing, reliability, QoS support, topology discovery, dynamic reconfiguration, energy efficiency, and clustered storage and fileserver. Research at any level of the network hierarchy (on-chip, intra-node, and cross-cluster) is welcome.
· Architectural and run-time system support for messaging, PGAS, shared memory, and other programming models.
· Design and implementation of standard or custom software communication layers for any or all parts of the network hierarchy.

Papers covering more than one of on-chip, intra-node, and cluster-wide communication networks are especially sought. Results of both theoretical and practical significance will be considered. Note, however, that papers on topics that are too far removed from scalable communication in HPC systems (e.g., mobile networks, intrusion detection, peer-to-peer networks, Grid/cloud computing) will be rejected without review.


The proceedings of this workshop will be published together with the proceedings of other IPDPS 2011 workshops by the IEEE Computer Society Press.

Authors of accepted papers at the CASS workshop will be invited to submit an extended version of their paper to contribute to a special issue of the Journal of Parallel and Distributed Computing journal (JPDC, impact factor 1.135). The contribution in that case should add significant novelty with respect to the paper published in CASS.

Paper Submissions

Submitted manuscripts may not exceed eight single-spaced pages using a 12-point font on 8½×11-inch pages, everything included (figures, tables, references, etc.). Manuscripts must be submitted electronically and in either PostScript or PDF format. Submissions will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. Submitted papers may not have appeared in or be under consideration for another workshop, conference, or journal.

CASS manuscript submissions are being handled by EDAS.

Important Dates
Paper submission: 3 January 2011
Notification of acceptance: 25 January 2011
Camera-ready papers due: 1 February 2011
Workshop date: 16 May 2011

All deadlines are set at 11:59 p.m. anywhere on Earth, except the camera-ready due date, which IPDPS sets as midnight PST (GMT–08:00).

Keynote speaker

We're pleased to announce that the CASS 2011 keynote address will be delivered by Matt Reilly of the Institute for Defense Analyses / Center for Computing Sciences. Dr. Reilly was one of the designers of Digital Equipment Corporation’s first 64-processor shared-memory multiprocessor and a co-founder and the Chief Engineer at SiCortex. His years of experience architecting everything from chips to massively parallel systems will provide CASS attendees with a unique perspective on communication architecture for scalable systems.

Workshop Organization

· Scott Pakin (Los Alamos National Lab, USA)
· Craig Stunkel (IBM Research, USA)
· José Flich (Universidad Politécnica de Valencia, Spain)

Publicity Chair:
· Gaspar Mora (Intel, USA)

Program Committee:
· Dennis Abts (Google, USA)
· Ahmad Afsahi (Queen’s University, Canada)
· Gheorghe Almasi (IBM Research, USA)
· Pavan Balaji (Argonne National Labs, USA)
· Davide Bertozzi (University of Ferrara, Italy)
· Taisuke Boku (University of Tsukuba, Japan)
· Darius Buntinas (Argonne National Laboratory, USA)
· Marcello Coppola (ST Microelectronics, France)
· Natalie Enright (University of Toronto, Canada)
· Holger Fröning (Heildeberg University, Germany)
· Ada Gavrilovska (Georgia Tech, USA)
· Torsten Hoefler (National Center for Supercomputing Applications, USA)
· John Kim (KAIST, Korea)
· Jesper Larsson (University of Vienna, Austria)
· Raymond Namyst (University of Bordeaux & INRIA, France)
· José Luis Sánchez (University of Castilla-La Mancha, Spain)
· Federico Silla (Universidad Politécnica de Valencia, Spain)
· Tor Skeie (Simula Research Labs, Norway)
· Gregory Thorson (SGI, USA)
· Keith Underwood (Intel, USA)
· Eitan Zahavi (Mellanox Technologies, Israel)

Steering Committee:
· D. K. Panda (Ohio State University, USA)
· José Duato (Universidad Politécnica de Valencia, Spain)

Additional Information

For more information on CASS 2011 or if you have any questions please contact the workshop organizers at the e-mail address listed at the bottom of this CFP.

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