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HipHaC 2011 : Second International Workshop on New Frontiers in High-performance and Hardware-aware Computing

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Link: http://capp.itec.uka.de/capp/conferences/hiphac11/
 
When Feb 13, 2011 - Feb 13, 2011
Where San Antonio, Texas, USA
Submission Deadline Nov 28, 2010
Notification Due Dec 19, 2010
Final Version Due Jan 14, 2011
Categories    high performance computing
 

Call For Papers

Workshop theme: Heterogeneity and reconfigurability in computer systems are growing. Multi- and manycore-based systems are complemented by coprocessors, accelerators, and reconfigurable units providing huge computational power. However, applications of scientific interest (e.g. in high-performance computing and numerical simulation) are not yet ready to exploit the available high computing potential. Different programming models, non-adjusted interfaces, and bandwidth bottlenecks complicate holistic programming approaches for heterogeneous architectures. In modern microprocessors, hierarchical memory layouts and complex logics obscure predictability of memory transfers or performance estimations.

This workshop aims at combining new aspects of parallel, heterogeneous, and reconfigurable microprocessor technologies with concepts of high-performance computing and, particularly, numerical solution methods. Compute- and memory-intensive applications can only benefit from the full hardware potential if all features on all levels are taken into account in a holistic approach.

Topics of interest for workshop submissions include (but are not limited to):

* Emerging hardware architectures
(multi-/manycores, GPUs, FPGAs, ...)
* High-performance heterogeneous, adaptive, and reconfigurable computing
* Parallelization strategies in hybrid and hierarchical setups
* Hardware-aware computing and code optimization strategies
* Virtualization and software layers for heterogeneous and reconfigurable platforms freeing programmers from dedicated hardware knowledge
* Architecture- and memory-aware approaches for parallel numerical applications, implementation, and algorithm design
* Programming models, compiler techniques, and code optimization strategies for parallel systems
* Autotuning concepts and run-time adaptivity
* Practice and experience of multi-/manycore programming and application aspects
* Performance evaluation of scientific applications on emerging hardware
* Tools for design, programming, and optimization

Submission guidelines: You are invited to submit papers not exceeding 8 double-column IEEE formatted pages (including up to 6 keywords and an abstract of no more than 350 words), describing original, unpublished recent work related to the workshop theme. Submissions must be in PDF format and handed in via EasyChair. If you wish a blind review to be performed, do not include the author's name and affiliation in the paper.

Papers will be published in printed form via KIT Scientific Publishing.

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