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FPGA 2011 : ACM/SIGDA International Symposium on Field-Programmable Gate Arrays


Conference Series : Field Programmable Gate Arrays
When Feb 27, 2011 - Mar 1, 2011
Where Monterey, CA
Submission Deadline Sep 20, 2010
Notification Due Nov 12, 2010
Final Version Due Dec 6, 2010
Categories    FPGA   reconfigurable computing

Call For Papers

The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is the premier conference for presentation of advances in all areas related to FPGA technology. For FPGA 2011, we are soliciting original submissions describing novel research and developments in the following (and related) areas of interest:

FPGA Architecture: Novel logic block architectures, combination of FPGA fabric and system blocks (DSP, processors, memories, etc.), design of routing fabric, I/O interfaces, new commercial architectures and architectural features.
FPGA Circuit Design: Novel FPGA circuits and circuit-level techniques, impact of process and design technologies, methods for analyzing and improving issues with soft-errors, leakage, static and dynamic power, clocking, power grid, yield, manufacturability, reliability, test; studies on future device technologies (e.g. nano-scale, 3D gate) for FPGAs.
CAD for FPGAs: Placement, routing, retiming, logic optimization, technology mapping, system-level partitioning, logic generators, testing and verification, CAD for FPGA-based accelerators, CAD for incremental FPGA design and on-line design mapping and optimization, CAD for modelling, analysis and optimization of timing and power.
High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific models, languages, tools, and techniques to facilitate the design, development, debugging, verification, and deployment of large-scale and high-performance FPGA-based applications and systems – e.g. DSP, networking or embedded system tools and methodologies.
FPGA-Based and FPGA-like computing engines: Compiled accelerators, reconfigurable computing, adaptive computing devices, systems and software, rapid-prototyping.
Design Studies: Innovative uses of FPGA fabric for computation, exploitation of FPGA features and architectures, optimization of FPGA-based cores (e.g. arithmetic, DSP, security, embedded processors, memory interfaces, or other functions).
Applications: Implementation of designs on FPGAs to achieve high-performance, low-power, or high-reliability. Novel design algorithms which take advantage of FPGA features. Application-domain studies to analyze or improve FPGA implementation for networking, DSP, embedded, audio/video, automotive, imaging and other relevant areas.
Panel Outlines: Topic proposals for the traditional Monday night Panel Session at FPGA.
Authors are invited to submit English language PDF of their paper or panel proposal by 20 September, 2010. Submitted papers will be considered for acceptance as a full paper (10 pages maximum), as a short paper (4 pages), or as a poster.

This year, FPGA will use a double-blind reviewing system. Manuscripts must not identify authors or their affiliations. Self-references should be shown as "Removed for blind review". Papers that identify authors will not be considered. Exceptions may be made for papers presenting new FPGA-related community infrastructure if the ability of reviewers to access that infrastructure is key to evaluating the paper. Please contact the Program Chair before submitting if you feel that it is not possible to avoid identifying paper authors.

The paper submission link will be available closer to the conference submission deadline.

All papers should use the ACM formatting templates available at:

Notification of acceptance will be sent by 12 November, 2010. The authors of accepted papers will be required to submit the final camera-ready copy by 6 December, 2010. A proceedings of the accepted papers will be published by ACM and included in the Annual ACM/SIGDA CD-ROM Compendium publication.

Address questions to: Katherine Compton, University of Wisconsin-Madison, Program Chair FPGA 2011
Department of of Electrical and Computer Engineering
University of Wisconsin-Madison
Madison, WI 53706
Phone : +1 608 265 3917
Email :
Organizing Committee

General Chair: John Wawrzynek, University of California, Berkeley
Program Chair: Katherine Compton, University of Wisconsin-Madison
Finance Chair: Peter Chung, Imperial College
Publicity Chair: Satnam Singh, Microsoft Research, Cambridge UK

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