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VLSICS 2025 : International Journal of VLSI design & Communication Systems

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Link: http://airccse.org/journal/vlsi/vlsics.html
 
When N/A
Where N/A
Submission Deadline Jul 6, 2025
Notification Due Aug 6, 2025
Final Version Due Aug 13, 2025
Categories    VLSI   design   wireless   sensor networks
 

Call For Papers

International Journal of VLSI design & Communication Systems (VLSICS)

Citations, h-index, i10-index of VLSICS

Citations 2484   h-index 25   i10-index 75

Scope and Topics

International journal of VLSI design & Communication Systems (VLSICS) is a bi monthly open access peer-reviewed journal that publishes articles which contribute new results in all areas of VLSI Design & Communications. The goal of this journal is to bring together researchers and practitioners from academia and industry to focus on advanced VLSI Design & communication concepts and establishing new collaborations in these areas. Authors are solicited to contribute to this journal by submitting articles that illustrate research results, projects, surveying works and industrial experiences that describe significant advances in the VLSI design & Communications.

Topics of interest include but are not limited to, the following

  • Design
  • VLSI Circuits
  • Computer-Aided Design (CAD)
  • Low Power and Power Aware Design
  • Testing, Reliability, Fault-Tolerance
  • Emerging Technologies
  • Post-CMOS VLSI
  • VLSI Applications (Communications, Video, Security, Sensor Networks, etc)
  • Nano Electronics, Molecular, Biological and Quantum Computing
  • Intellectual Property Creating and Sharing
  • Wireless Communications

Paper Submission

Authors are invited to submit papers for this journal through Email: vlsicsjournal@airccse.org or through Submission System. Submissions must be original and should not have been published previously or be under consideration for publication while being evaluated for this Journal.

Important Dates

 

Submission Deadline:July 06, 2025
Authors Notification: August 06, 2025
Final Manuscript Due: August 13, 2025
Publication Date:Determined by the Editor-in-Chief

Current Issue


June 2024, Volume 15, Number 1/2/3

Detection of Module Integration Errors in Hierarchical Circuit Designs
Nicholas Dematteis, Jesus Godinez, Gina Rhoads, and Maddu Karunaratne, University of Pittsburgh, USA

Power Evaluation of MIPS Architecture using Clock Gating Technique on FPGAs
V.Prasanth1, K.Babulu1, and M.Kamaraju2, 1JNTUGV, India, 2Gudlavalleru Engineering College, India

April 2023, Volume 14, Number 1/2

Mighty Macros and Powerful Parameters: Maximizing Efficiency and Flexibility in HDL Programming
Muneeb Ulla Shariff, Vineeth Kumar Veepuri, Nancy Dimri and Mahadevaswamy B N, Mirafra Technologies, India

An Efficient Segmented Random Access Scan Architecture with Test Compression
Maddumage Karunaratne1 and Bejoy G. Oomman2, 1University of Pittsburgh, USA, 2Genesys Testware/Broadcom Inc., USA

December 2022, Volume 13, Number 1/2/3/4/5/6

Approximate Arithmetic Circuit Design for Error Resilient Applications
Viraj Joshi and Pravin Mane, Bits Pilani, K.K. Birla Goa Campus, Goa, India

Related Journal

Associate Editors

Editorial Board Members

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