Memory-device manufacturing, memory-architecture design, and the use of memory technologies by application software all profoundly impact today’s and tomorrow’s computing systems, in terms of their performance, function, reliability, predictability, power dissipation, and cost. Existing memory technologies are seen as limiting in terms of power, capacity, and bandwidth. Emerging memory technologies offer the potential to overcome both technology- and design-related limitations to answer the requirements of many different applications. Our goal is to bring together researchers, practitioners, and others interested in this exciting and rapidly evolving field, to update each other on the latest state of the art, to exchange ideas, and to discuss future challenges. Please visit memsys.io for more information.

Areas of Interest
Previously unpublished papers containing significant novel ideas and technical results are solicited. Papers that focus on system, software, and architecture level concepts specifically memory-related, i.e. topics outside of traditional conference scopes, will be preferred over others (e.g., the desired focus is away from pipeline design, processor cache design, prefetching, data prediction, etc.). Symposium topics include, but are not limited to, the following:

Memory-system design from both hardware and software perspectives
Memory failure modes and mitigation strategies
Memory and system security issues
Memory for embedded and autonomous systems (e.g., automotive)
Operating system design for hybrid/nonvolatile memories
Technologies including flash, DRAM, STT-MRAM, 3DXP, etc.
Memory-centric programming models, languages, optimization
Compute-in-memory and compute-near-memory technologies
Data-movement issues and mitigation techniques
Interconnects to support large-scale data movement
Algorithmic & software memory-management techniques
Emerging memory technologies, their controllers, and novel uses
Interference at the memory level across datacenter applications
Issues in the design and operation of large-memory machines
In-memory databases and NoSQL stores

Post-CMOS scaling efforts and memory technologies to support them, including cryogenic, neural, and heterogeneous memories To reiterate, papers that focus on topics outside the scope of traditional architecture conferences will be preferred over others.

Submissions and Presentations
Our primary goal is to showcase interesting ideas that will spark conversation between disparate groups—to get applications people, operating systems people, system architecture people, interconnect people and circuits people to talk to each other. We accept extended abstracts, position papers, and/or full research papers, and each accepted submission is given a 20-minute presentation time slot. All accepted papers will be published in the ACM Digital Library and IEEE Xplore.

Venue
The conference will be held at The Westin Arlington Gateway in Arlington VA.

IMPORTANT
DATES

Submission:
29 May, 2020 (+7 days)*
Notification:
31 July, 2020
Camera-Ready:
14 August, 2020

*Automatic 1-week submission extension


SUBMISSION FORMATS

1–2 page Abstracts
5–6 page Position Papers 10+ page Research Papers

Conference paper format, ACM 'sigconf' proceedings template, blind submission (no authors listed), up to 16 pages long

Keynotes & Panelists
Yitzhak Birk, Technion
Chen Ding, University of Rochester
Dave Dunning, Qualcomm
Matthias Jung, Fraunhofer IESE
John Leidel, Tactical Computing Labs
Petar Radojkovic, BSC
Arun Rodrigues, Sandia National Labs
Kevin Rudd, DoD
Robert Trout, Micron


Organizers

Bruce Jacob, University of Maryland Kathy Smiley, Memory Systems

Ameen Akel, Micron
James Ang, PNNL
Abdel-Hameed Badawy, NMSU
Jonathan Beard, Arm
Bruce Childers, University of Pittsburgh
Zeshan Chishti, Intel
Bruce Christenson, Intel
David Donofrio, Tactical Computing Labs
Dietmar Fey, FAU Erlangen-Nürnberg
Maya Gokhale, LLNL