The International Workshop on Logic and Synthesis is the premier forum for research in
synthesis, optimization, and verification of integrated circuits ans systems. Research on logic synthesis for emerging technologies and for novel computing platforms, such as nanoscale systems and biological systems, is also strongly encouraged. The workshop encourages early dissemination of ideas and results. The workshop accepts complete papers highlighting important new problems in the early stages of development, without providing complete solutions. The emphasis is on novelty and intellectual rigor.
Topics of interest include, but are not limited to: hardware synthesis and optimization;
software synthesis; hardware/software co-synthesis; power and timing analysis; testing, validation and verification; synthesis for reconfigurable architectures; hardware compilation for domain-specific languages; and design experiences. Submissions on modeling, analysis and synthesis for emerging technologies and platforms are particularly encouraged.

Call for regular papers: Only complete papers with original and previously unpublished
material are permitted. Submissions must be no longer than 8 pages, double column, 10-
point font. Accepted papers are distributed only to IWLS participants. The workshop format
includes paper presentations, posters, invited talks and social coffee breaks. Submissions are made electronically through EasyChair. Please see the workshop website for instructions.

Organizing Committee:
General Chair Luca Amaru Synopsys, USA
Program Committee Chairs Eleonora Testa / Valentina Ciriani Synopsys, USA / University of Milan, IT
Program Contest Chairs Alan Mishchenko / Satrajit Chatterjee University of California Berkeley, USA / Google, USA
Special Session Chair Cunxi Yu Univerisy of Utah, USA
Finance Chair Zhufei Chu Ningbo University, China
Proceedings Chair Walter Lau Neto Univerisy of Utah, USA
Publicity Chair Augusto Neutzling Cadence, UK
Virtual Chair Giulia Meuli Synopsys, IT