Prolog
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GPUs are evolving as massively threaded vector machines. While the primary design goal of the GPUs is efficient processing of the graphics stack, the massive parallelism available in these chips has lately opened up the possibility of carrying out general purpose computing on them. This computing paradigm is called GPGPU. Although manually mapping regular data parallel applications on GPUs has been explored quite extensively, making truly general purpose computing feasible on GPUs requires answering a number of important questions. This half-day workshop aims at bringing together the researchers and practitioners in this rapidly evolving area with a goal of addressing issues related to programming languages, programming models, compiler
optimizations, and architecture to make GPGPU a conducive execution environment for regular as well as irregular applications. The topics of interest include, but are not limited to, the following.

+ New GPU architecture features to enhance GPGPU
+ Memory system innovations to enhance GPGPU
+ Implications of GPGPU on memory consistency models
+ Architecture support for single-chip CPU-GPU integration
+ Programming models and language support for GPGPU
+ Compiler Optimization for GPGPU
+ Debugging/Performance visualization tools for GPGPU
+ Efficient synchronization support for GPGPU
+ Performance evaluation of irregular applications on GPUs
+ Energy-efficiency studies of GPGPU
+ GPGPU benchmarks

Call for papers
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The workshop invites submissions featuring unpublished results. The submissions must not exceed ten pages in two-column IEEE transaction style. The workshop will feature one invited keynote and a number of contributed papers selected from the submissions. All the papers and presentations will be made available online. However, publication in this workshop does not preclude later publication in regular conferences and journals.

Submission instructions
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Please send your submission in PDF format to the following email address:
gpgpu@cse.iitk.ac.in
You will receive a confirmation email in response to your submission.


Important dates
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Submission deadline: October 20, 2009
Acceptance notification: November 20, 2009
Final paper deadline: December 5, 2009

Organizing committee
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Mainak Chaudhuri, IIT Kanpur
Kalyan Muthukumar, Intel

Program committee
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Rajesh Bordawekar, IBM
Mainak Chaudhuri, IIT Kanpur
Jonathan Cohen, nVIDIA
Michael Garland, nVIDIA
Milind Girkar, Intel
Ajay Joshi, Intel
David Kaeli, Northeastern University
Subodh Kumar, IIT Delhi
Dinesh Manocha, UNC Chapel Hill
Andreas Moshovos, University of Toronto
Kalyan Muthukumar, Intel
P. J. Narayanan, IIIT Hyderabad
Ben Sander, AMD
Karu Sankaralingam, UW-Madison
John Stone, UIUC
Kumar Vemuri, Intel
Peng Wu, IBM