As intelligent systems expand into diverse environments—from IoT sensors to autonomous devices—traditional applications, architectures, and methodologies face new limits. The increasing demand for real-time, low-power, and context-aware intelligence at the edge is pushing the boundaries of what current computing systems can deliver. Edge devices must now operate under tight constraints of memory, latency, and energy, while still supporting sophisticated AI workloads. These challenges call for a rethinking of how we design, deploy, and optimize intelligent systems at the edge.

The EDGE-X 2025 workshop, part of the Fifth International AI-ML Systems Conference (AIMLSys 2025), aims to address the critical challenges and opportunities in next-generation edge computing. EDGE-X explores innovative solutions across various domains, including on-device learning and inferencing, ML/DL optimization approaches to achieve efficiency in memory/latency/power, hardware-software co-optimization, and emerging beyond von Neumann paradigms including but not limited to neuromorphic, in-memory, photonic, and spintronic computing. The workshop seeks to unite researchers, engineers, and architects to share ideas and breakthroughs in devices, architectures, algorithms, tools, and methodologies that redefine performance and efficiency for edge computing.

EDGE-X 2025 invites submissions of original research papers, case studies, and review articles in the field of low-power efficient edge AI. The workshop seeks to foster discussions on a wide range of topics, including but not limited to:

* Ultra-Efficient Machine Learning – TinyML, binary/ternary neural networks, federated learning, model pruning, compression, quantisation, and edge-training
* Hardware-Software Co-Design – RISC-V custom extensions for edge AI, non-von-Neumann accelerators (e.g., in-memory compute, FPGAs)
* Beyond CMOS & von Neumann Paradigms – Neuromorphic computing (spiking networks, event-based sensing), inmemory/compute architectures (memristors, ReRAM), photonic integrated circuits, spintronic and quantum-inspired devices
* System-Level Innovations – Near-/sub-threshold computing, power-aware OS/runtime frameworks, approximate computing for error-tolerant workloads
* Tools & Methodologies – Simulators for emerging edge devices (photonic, spintronic), energy-accuracy trade-off optimisation, benchmarks for edge heterogeneous platforms
* Use Cases & Deployment Challenges – Self-powered/swarm systems, ruggedised edge AI, privacy/security for distributed intelligence, sustainability and lifecycle management
* Interdisciplinary approaches & collaborations in low-power high-efficiency edge AI research for edge computing.

Papers should be at most 4 pages, including title, abstract, figures and results, but excluding references, and not published or under review elsewhere. Papers should be prepared as per IEEE conference proceedings format (link: https://www.ieee.org/conferences/publishing/templates). Please submit your papers through Microsoft CMT (link: https://cmt3.research.microsoft.com/AIMLSys2025/). All accepted workshop full papers will be included in the IEEE proceedings. At least one author of each accepted paper must register for the conference and present the paper. In addition, no-shows of accepted papers at the workshop will result in those papers NOT being included in the proceedings.