Recent trends in the microprocessor industry have important ramifications for the design of the next generation of computing systems. By increasing number of cores, it is possible to improve the performance while keeping the power consumption unchanged. This trend has reached the deployment stage in computing systems ranging from small ultramobile devices to large telecommunication servers. It is also expected that the number of cores in these systems rises dramatically in the near future.
On-chip communication architecture plays a crucial role to enhance the system reliability, power, and performance characteristics. In order to enable multi-core and many-core systems to provide significant performance benefits and maximize utilization of on-chip resources, many technical challenges associated with on-communication architecture should be addressed. The goal of this special session is to bring together research and industry experiences focused on architectures for on-chip communication domain.

This special session addresses all aspects of on-chip communication architecture design and test for multi-core and many-core systems. It presents new ideas in the on-chip communication field such as theory and modeling, scalable and fault tolerant design approaches and frameworks, tools and applications, analysis and comparison, design techniques and emerging implementations.

Authors are invited to submit high quality papers representing original work from both the academia and industry in (but not limited to) the following topics:

* Design space exploration and tradeoff analysis
* Novel bus and networks-on-chip architectures, including cluster interconnects
* Switching, buffering, topology, routing, and mapping algorithms
* Flow control and congestion management
* Virtualization, QoS, guaranteed throughput and on-chip real time communication
* Router microarchitecture
* Power and energy issues
* Dependable architectures
* On-chip communication architectures for the dark silicon era
* Fault tolerance and reliability issues
* Dynamic on-chip network reconfiguration
* Modeling and evaluation
* On-chip communication support for memory and cache access
* 3D on-chip architectures, emerging technologies and new design paradigms
* Timing, synchronous/asynchronous on-chip communication
* Interconnection physical link design
* Testing and verification of on-chip interconnection devices
* System prototyping
* Industrial practices and case studies


Session Chairs:

Hannu Tenhunen, University of Turku, Finland & Royal Institute of Technology, Sweden
Pasi Liljeberg, University of Turku, Finland
Amir-Mohammad Rahmani, University of Turku, Finland


Submission guidelines:

Submissions must be in PDF and should not exceed 8 pages. The submission must adhere to the two-column IEEE style using 10 pt. fonts. The page limit includes all figures and references. All pages should be numbered. Please make use of the following link to help you in the preparation and submission of your final manuscript: http://www.computer.org/portal/web/cscps/submission


Publication:

Proceedings will be published by the IEEE CPS in the same volume of the main track. Authors of accepted papers are expected to register and present their papers at the symposium. Symposium proceedings will be included in the Computer Society Digital Library CSDL and IEEE Xplore. All CPS conference publications are also submitted for indexing to EI’s Engineering Information Index, Compendex, and ISI Thomson’s Scientific and Technical Proceedings, ISTP/ISI Proceedings, and ISI Thomson.

Authors of selected papers will be invited to submit extended article versions to one of the ISI-indexed high-quality journals.


Contacts:

Amir-Mohammad Rahmani
Department of Information Technology
University of Turku, Finland
E-mail: amir(-dot-)rahmani(-at-)utu(-dot-)fi
Tel: (+358) 443-462629