CICC: Custom Integrated Circuits Conference

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2014 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
CICC 2013 IEEE Custom Integrated Circuits Conference
Sep 23, 2013 - Sep 25, 2013 San Jose Apr 25, 2013
CICC 2012 IEEE Custom Integrated Circuits Conference
Sep 9, 2012 - Sep 12, 2012 San Jose, USA Apr 7, 2012
CICC 2011 IEEE Custom Integrated Circuits Conference
Sep 18, 2011 - Sep 21, 2011 San Jose, CA, USA Apr 18, 2011
CICC 2008 IEEE Custom Integrated Circuits Conference
Sep 21, 2008 - Sep 24, 2008 San Jose, CA, USA Apr 7, 2008
 
 

Present CFP : 2013

IEEE CICC is sponsored by the IEEE Solid-State Circuits Society
and technically co-sponsored by the IEEE Electron Devices Society
DoubleTree Hotel
San Jose, California
September 23 - 25, 2013
The IEEE Custom Integrated Circuits Conference (CICC) is the premier conference devoted to IC development. CICC showcases original, first-published innovative analog and digital circuit techniques covering a broad spectrum of technical topics. It is a forum for circuit, IC and SoC designers, CAD developers, manufacturers and ASIC users. CICC is the conference to find out how to solve design problems and improve circuit design and chip design techniques.
Conference Highlights
Technical Papers
Education on new, state-of-the-art developments is the core of the CICC technical program. Over 160 papers, addressing a broad range of circuits, applications, design techniques, tools, test, reliability, and system-on-a-chip, will be presented. Awards for Best Paper will be given in both the regular and student submission categories. Top-rated CICC papers are also eligible to be considered for publication in a special issue of the IEEE Journal of Solid State Circuits.
Poster Presentations
CICC will include poster presentations as well as traditional lecture presentations. Poster presentations are a unique opportunity for a greater depth of discussion between authors and the CICC audience.
Panels
Leaders from the IC industry debate key issues and controversial topics in panel sessions. CICC panels are well known for their lively and thought-provoking discussion and audience participation.
Educational Sessions
Educational sessions are included in the conference fee and strategically placed so that the attendees can get a basic understanding of the topics before going more in depth with the technical papers. These tutorials, instructed by recognized invited speakers, are among the best in the industry. They are valuable opportunities to refresh key skills in traditional circuit-design methods and acquire knowledge in vital new areas in analog, digital, and RF integrated circuit IC design.
Exhibits
Semiconductor manufacturers, software tool suppliers, silicon IP providers, design-service houses, and technical book publishers offer displays and demonstrations of their products.
Conference Events
Our Welcome Reception, Conference Reception and Conference Luncheon complement the technical program of CICC and provide additional opportunities for discussion and peer networking in a relaxed environment. The Poster Presentations will also be a major conference event, attended by all and accompanied by food and beverage.
CICC is soliciting papers in the following areas:
Analog Circuit Design: Data Converters-Nyquist and oversampled, mixed signal analog/digital applications, analog sensor processing applications, low voltage and low power analog, deep submicron issues in analog design. Blocks for analog systems-amplifiers, sample-holds, voltage references and regulators, filters continuous and discrete, non linear analog blocks, novel clock generation.
Systems on Chip and 3D: Architectures, micro-architectures, methodologies and infrastructures for SoC or multi-dimensional designs realized in silicon. Design challenges and solutions in advanced process nodes. General purpose or application specific 3D / 2.5D multi-chip designs. Innovative, advanced, complex or high performance circuits or design techniques for digital or mixed signal SoCs, ASICs or FPGAs.
Memory: Circuits, architectures, device technologies, and manufacturing solutions addressing all memory aspects such as power-performance-density trade-offs, Vmin, resiliency, endurance, data retention, process variations, and reliability. Of interest are both mainstream and emerging memories including but not limited to SRAM, CAM, ROM, e/DRAM, Floating Gate, MRAM, RRAM, PCM, OTP, and 3D memories used in consumer electronics as well as novel applications.
Biomedical, Actuators, MEMS, and Sensors: Advanced ICs for biomedical, aerospace, automotive, energy, environment, and security applications. Interface circuits for emerging technologies in medicine, actuators, MEMS, and sensors are of particular interest. Examples include biosensors and devices and networks, nanotechnology, microchemical sensors, image sensors, OLEDs, DNA microarrays, micro- and nanofluidic chips, novel display technologies and organic circuitry.
IC Manufacturing: Special focus on challenges of and alternatives to CMOS scaling, Design for Manufacturability, specialty manufacturing techniques, and design / technology interaction. Advanced manufacturing techniques using any combination of bulk/SOI CMOS, non-silicon, and photonic technologies. Evolving chip packaging such as chip stacking, lead-free, flip-chip, and System-in-Package. Tutorial content and impact to the design community is encouraged.
Power Management:
Circuit and system architectures for power management and power consumption optimization. Advanced circuit topologies and innovations in switching / linear regulators, low power design, energy scavenging, wireless and peripheral charging, battery metering, digital control, dynamic power control, and other topical areas related to the challenges of efficient power generation, distribution, and utilization.
Simulation and Modeling: Simulation/modeling techniques and methodologies for device-and circuit-level analysis, design and verification of analog, RF, memory, and mixed-signal circuits. Statistical and reliability modeling and simulation. Effects of FinFETs and FD-SOI on circuit level performance and variability. Compact models for active and passive devices. Behavioral modeling and simulation. PDK generation and validation. Parasitic extraction and reduction. Modeling and simulation of 3D ICs. Signal-integrity modeling and simulation. Package modeling.
Test, Debug, and Reliability: Debug techniques. DFT (design for test) for digital, memory, analog/mixed signal circuits, equalizers, CDR, high speed I/O, MEMS, RF, and photonic ICs. Design techniques for high reliability applications. Reliability concerns in leading edge technologies, such as soft errors. Innovations in ESD protection. Issues of testability and constraints due to protection of intellectual property or system security.
Wireline Communications: Circuits and systems for electrical and optical communications, including: serial links, backplanes, high-speed memory and graphics interfaces, intra-chip and chip-to-chip interconnects, peripheral I/O buses, photonic transceivers; circuit blocks including serializers, deserializers, equalizers, link-related clocking (PLL, DLL, and CDR), electro-optical conversion (TIA, laser/modulator drivers).
Wireless Designs: Integrated wireless transceiver architectures and sub-circuits for cellular, connectivity, broadband and low-power communication, millimeter-waves and Terahertz, biomedical, smart antennae, MIMO, RF MEMS, software-defined and cognitive radio. Papers on RF circuit solutions targeting emerging wireless applications (LTE, WLAN 802.11ac) are particularly encouraged.
Submission of Papers
Paper Submission deadline is April 25, 2013
Papers must report original and previously unpublished work, including specific results. Papers may be up to 4 pages in length including illustrations, charts, tables and references. Successful submissions concisely explain how the work advances the state of the art and include schematics, measured results, and technical detail sufficient to be understood. Circuit-design papers intended for traditional lecture presentation must include measured experimental results that substantiate performance claims. Circuit-design papers using only simulation to substantiate performance claims are usually rejected for traditional lecture presentation, but may be considered for poster presentation.
Papers are submitted electronically. Prior to preparing your paper for electronic submission, please read the paper preparation and submission guidelines on the CICC website (www.ieee-cicc.org). The submission instructions are available and the submission page will be active on March 5. Go to the CICC website at www.ieee-cicc.org and click on Papers and Presentations.
When submitting a paper, please indicate a preference for traditional lecture or poster presentation, although CICC may assign presentations to either category.
Deadline for submission of technical papers is April 25, 2013. Appropriate company and government clearances MUST be obtained prior to submission. AUTHORS MUST SUBMIT a completed copyright form at the time of paper submission. If a copyright form is not received with the submission, the paper will not be reviewed. Authors of accepted papers will be notified by email by June 25, 2013.
ACCEPTED PAPERS WILL BE PRINTED IN THE PROCEEDINGS WITHOUT OPPORTUNITY FOR FURTHER CHANGE.
Accepted papers will be used for publicity purposes and portions of these papers may be quoted in pre-conference magazine articles and also via the Web. If this is not acceptable, authors must email CICC at cicc@his.com to decline publicity.
Papers for Poster Presentation
Poster presentations encourage in-depth discussions with the audience and are ideal for the presentation of ongoing research. The Poster Session will be held in an extended informal setting accompanied by food, inviting all CICC attendees to engage in discussions with authors. The acceptance criteria for papers for poster presentation are identical to those for traditional lecture presentation except that the requirement for measured experimental results may be relaxed for papers intended for poster presentation.
For Further Information
For complete author kit instructions, registration information, and general inquiries visit the CICC website at www.ieee-cicc.org or contact the Conference Office: IEEE Custom Integrated Circuits Conference, 19803 Laurel Valley Place, Montgomery Village, MD 20886, Telephone: 301/527-0900 x1, Fax: 301/527-0994, email: melissaw@widerkehr.com, web page: http://www.ieee-cicc.org.
Visit the CICC web site for complete instructions on submitting a paper.
Web address: www.ieee-cicc.org
Submission Deadline: April 25, 2013
The IEEE Custom Integrated Circuits Conference is sponsored by:
The Institute of Electrical and Electronics Engineers, Inc.
IEEE Solid-State Circuits Society
And technically sponsored by the IEEE Electron Devices Society
ORGANIZING COMMITTEE
General Chair: Aurangzeb Khan, Altia Systems
aurangzeb.khan@altiasystems.com
Conference Chair: Philippe Jansen, Texas Instruments philippe.jansen@ti.com
Technical Program Chair: Ramesh Harjani, University of Minnesota
harjani@umn.edu
Educational Session Chair: Howard Luong, Hong Kong University of Science & Technology
eeluong@ece.ust.hk
Panel Chair: Kimo Tan, Analog Devices
kimo.tam@analog.com
Sponsorship Chair: Alessandro Piovaccari, Silicon Labs
piovac@ieee.org
Exhibits Chair: Trent McConaghy Solido Design
trentmc@solidodesign.com
Publicity Chair: Ken Suyama, Epoch Microelectronics
ken.suyama@epochmicro.com
Best Paper Chair: Ron Kapusta, Analog Design
ron.kapusta@analog.com
Solid State Circuits Society Rep: Tom Andre, Everspin
Tom.andre@everspin.com
Treasurer: Rakesh Patel, Consultant, rakeshp@pacbell.net
Conference Coordinator: Melissa Widerkehr, Widerkehr & Assoc.
melissaw@widerkehr.com
 

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