RAW: Reconfigurable Architectures Workshop



Past:   Proceedings on DBLP

Future:  Post a CFP for 2017 or later   |   Invite the Organizers Email


All CFPs on WikiCFP

Event When Where Deadline
RAW 2016 Reconfigurable Architectures Workshop
May 23, 2016 - May 24, 2016 Chicago, Illinois USA Jan 8, 2016 (Jan 4, 2016)
RAW 2015 22nd Reconfigurable Architectures Workshop
May 25, 2015 - May 25, 2015 Hyderabad, India Jan 20, 2015
RAW 2014 21st Reconfigurable Architectures Workshop
May 18, 2014 - May 19, 2014 Phoenix, USA Dec 9, 2013
RAW 2013 Reconfigurable Architectures Workshop
May 20, 2013 - May 21, 2013 Boston, USA Dec 28, 2012
RAW 2012 19th Reconfigurable Architectures Workshop
May 21, 2012 - May 22, 2012 Shanghai, China Jan 12, 2012
RAW 2010 17th Reconfigurable Architectures Workshop
Apr 19, 2010 - Apr 20, 2010 Atlanta, USA Nov 15, 2009
RAW 2009 Reconfigurable Architectures Workshop
May 25, 2009 - May 26, 2009 Rome, Italy Oct 31, 2008
RAW 2008 15th Reconfigurable Architectures Workshop
Apr 14, 2008 - Apr 15, 2008 Miami, Florida, USA Oct 8, 2007

Present CFP : 2016

The 23rd Reconfigurable Architectures Workshop (RAW 2016) will be held in Chicago, Illinois USA in May 2016. RAW 2016 is associated with the 30th IEEE International Parallel & Distributed Processing Symposium (IPDPS 2016) and is sponsored by the IEEE Computer Society Technical Committee on Parallel Processing. The workshop is one of the major meetings for researchers to present ideas, results, and on-going research on both theoretical and practical advances in Reconfigurable Computing.

A reconfigurable computing environment is characterized by the ability of underlying hardware architectures or devices to rapidly alter (often on the fly) the functionalities of their components and the interconnection between them to suit the problem at hand. The area has a rich theoretical tradition and wide practical applicability. There are several commercially available reconfigurable platforms (FPGAs and coarse-grained devices) and many modern applications (including embedded systems and HPC) use reconfigurable subsystems. An appropriate mix of theoretical foundations and practical considerations, including algorithms architectures, applications, technologies and tools, is essential to fully exploit the possibilities offered by reconfigurable computing. The Reconfigurable Architectures Workshop aims to provide a forum for creative and productive interaction for researchers and practitioners in the area.

Authors are invited to submit manuscripts of original unpublished research in all areas of reconfigurable systems, including architectures, algorithms, applications, software and cross-cutting areas.

Topics of interest include, but are not limited to:

Architectures & Algorithms

· Theoretical Interconnect and Computation Models

· Algorithmic Techniques and Mapping

· Run-Time Reconfiguration Models and Architectures

· Emerging Technologies (optical models, 3D Interconnects, devices)

· Bounds and Complexity Issues

· Analog Arrays

Reconfigurable Systems & Applications

· Reconfigurable Accelerators (HPC, Bioinformatics, Acceleration Applications in Finance, Data Mining, Big Data, and Analytics)

· Embedded systems and Domain-Specific solutions (Digital Media, Gaming, Automotive applications)

· FPGA-based MPSoC and Multicore

· Distributed Systems and Networks

· Wireless and Mobile Systems

· Emerging applications (Organic Computing, Biology-Inspired Solutions)

· Critical issues (Security, Energy efficiency, Fault-Tolerance)

Software & Tools

· Operating Systems and High Level Synthesis

· High-Level Design Methods (Hardware/Software Co-design, Compilers)

· System Support (Soft Processor Programming)

· Runtime Support

· Reconfiguration Techniques (Reusable Artifacts)

· Simulations and Prototyping (Performance Analysis, Verification Tools)

Submission Guidelines:

All manuscripts will be reviewed by at least three members of the program committee. Submissions should be a complete manuscript or, in special cases, may be a summary of relevant work. The manuscript should be not exceed 8 single-spaced, double-column pages using 10-point size font on 8.5X11 inch pages (IEEE conference style) including references, figures and tables. Papers are to be submitted through EDAS. Submitted papers should not have appeared in or be under consideration for a different workshop, conference or journal. It is also expected that all accepted papers (regular or poster) will be presented at the workshop by one of the authors.


IEEE CS Press will publish the IPDPS symposium and workshop abstracts as a printed volume. The complete symposium and workshop proceedings will also be published by IEEE CS Press as a CD-ROM disk and will be available in the IEEE Digital Library.

Related Resources

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HEART 2024   14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies
SS@CSNDSP 2024   Special Session on Reconfigurable Intelligent Surfaces for Communications and Sensing @ CSNDSP2024
PACT 2024   The International Conference on Parallel Architectures and Compilation Techniques
ReacTS 2024   International Workshop on Reconfigurable Transition Systems: Semantics, Logics and Applications
DASIP 2025   Workshop on Design and Architectures for Signal and Image Processing
HiPEAC 2025   High Performance Embedded Architectures and Compilers
HPEC 2024   IEEE High Performance Extreme Computing
ICWI 2024   23rd International Conference WWW/Internet
Euro-PAR 2024   30th International European Conference on Parallel and Distributed Computing