Paper Submission Deadline: March 10th, 2025
Acceptance Notification: May 10th, 2025
Submission of Final Version: May 30th, 2025
Special Session Proposal Deadline: March 15th, 2025


The 2025 Symposium explores emerging trends and novel ideas and concepts covering a broad range of topics in the area of VLSI: from VLSI circuits, systems and design methods, to system level design issues, to bringing VLSI design to new areas and technologies such as nano- and molecular devices, security, artificial intelligence, and Internet-of-Things, etc. Future design methodologies and new EDA tools are also a key topic at the Symposium. Over three decades the Symposium has been a unique forum promoting multidisciplinary research and new visionary approaches in the area of VLSI, bringing together leading scientists and researchers from academia and industry. Accepted papers will be submitted for inclusion into IEEE Xplore subject to meeting IEEE Xplore’s scope and quality requirements. Selected high quality papers will be further invited for submission to a journal special issue. The Symposium has established a reputation in bringing together well-known international scientists as invited speakers. The emphasis on high quality will continue at this and future editions of the Symposium.


Contributions are sought in the following tracks:
Circuits, Reliability, and Fault-Tolerance (CRT):
Analog/mixed-signal circuits design and testing, RF and communication circuits, adaptive circuits and interconnects, design for testability, online testing techniques, static and dynamic defect- and fault- recoverability, variation aware design, VLSI aspects of sensor and sensor network.
Computer-Aided Design and Verification (CAD):
Hardware/software co-design, logic and behavioral synthesis, simulation and formal verification, physical design, signal integrity, power and thermal analysis, statistical approaches.
Digital Circuits and FPGA based Designs (DCF):
Digital circuits, chaos/neural/fuzzy-logic circuits, high speed/low-power circuits, energy efficient circuits, near and sub-threshold circuits, memories, FPGA designs, FPGA based systems.
Emerging and Post-CMOS Technologies (EPT):
Nanotechnology, molecular electronics, quantum devices, optical computing, spin-based computing, biologically-inspired computing, CNT, SET, RTD, QCA, reversible logic, and CAD tools for emerging technology devices and circuits.
System Design and Security (SDS):
Structured and custom design methodologies, microprocessors/micro-architectures for performance and low power, embedded processors, analog/digital/mixed-signal systems, NoC, power and temperature aware designs, hardware security, cryptography, watermarking, and IP protection, TRNG and security-oriented circuits, PUF circuits.
VLSI for Applied and Future Computing (AFC):
Neuromorphic and brain-inspired computing, quantum computing, circuits and architectures for machine learning and artificial intelligence, methodologies for on-chip learning, deep learning acceleration techniques, applications for and use-cases of learning systems, sensor and sensor network, electronics for Internet of Things and smart medical devices.

Author Guidelines
Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. Previously published papers or papers currently under review for other conferences/journals should NOT be submitted and will not be considered. To enable blind review, the author list should be omitted from the main document. The manuscript as a single PDF is to be submitted online through Easychair. The manuscript as a single PDF is to be submitted online through Easychair. The IEEE Manuscript Template for Conference Proceedings should be used, which can be found here: https://www.ieee.org/conferences/publishing/templates.html