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Present CFP : 2017
The 35th IEEE International Conference on Computer Design
November 5 - 8, 2017
Boston Area, Massachusetts, USA
The IEEE International Conference on Computer Design encompasses a wide range of topics in the research, design, and implementation of computer systems and their components. ICCD’s multi-disciplinary emphasis provides an ideal environment for developers and researchers to discuss practical and theoretical work covering systems and applications, computer architecture, veriﬁcation and test, design tools and methodologies, circuit design, and technology.
We especially encourage submissions that look forward to future systems and technologies. Manuscripts describing original work on any topic from the scope of ICCD are welcome. Authors are asked to submit technical papers in accordance to the author’s instructions in one of the following five conference tracks:
Computer Systems and Applications: Advanced computer architecture for general and application-specific enhancement; Software design for embedded, mobile, general-purpose, cloud, and high-performance platforms; IP and platform-based designs; HW/SW codesign; Modeling and performance analysis; Support for security, languages and operating systems; Hardware/software techniques for embedded systems; Application-specific and embedded software optimization; Compiler support for multi-threaded and multi-core designs; Memory system and network system optimization; On-chip and system-area networks; Support for communication and synchronization.
Processor Architecture: Microarchitecture design techniques for uni- and multi-core processors: instruction-level parallelism, pipelining, caching, branch prediction, multithreading; Techniques for low-power, secure, and reliable processors; Embedded, network, graphic, system-on-chip, application specific and digital signal processor design; Hardware support for processor virtualization; Real-life design challenges: case studies, tradeoffs, postmortems.
Logic and Circuit Design: Circuits and design techniques for digital, memory, analog and mixed-signal systems; Circuits and design techniques for high performance and low power; Circuits and design techniques for robustness under process variability and radiation; Design techniques for emerging process technologies (MEMs, spintronics nano, quantum, flexible electronics); Asynchronous circuits; Signal processing, graphic processor and arithmetic circuits.
Electronic Design Automation: High-level, logic and physical synthesis; Physical planning, design and early estimation for large circuits; Automatic analysis and optimization of timing, power and noise; Tools for multiple-clock domains, asynchronous and mixed timing methodologies; CAD support for FPGAs, ASSPs, structured ASICs, platform-based design and NOC; DfM and OPC methodologies; System-level design and synthesis; Tools and design methods for emerging technologies (MEMs, spintronics, nano, quantum).
Test, Verification and Security: Design error debug and diagnosis; Fault modeling; Fault simulation and ATPG; Analog/RF Testing; Statistical Test Methods; Large volume yield Analysis and Learning; Fault tolerance; DFT and BIST; Functional, transaction-level, RTL, and gate-level modeling and verification of hardware designs; Equivalence checking, property checking, and theorem proving; Constrained-random test generation; High-level design and SoC validation. Hardware security primitives; Side channel analysis; Logic and microarchitectural countermeasures; Hardware security for IoT; Interaction between VLSI test and trust.
ICCD steering committee is soliciting proposal for ICCD 2018 and beyond. Please send in your proposal to kee.sup.kim at ieee dot org.