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Present CFP : 2016
CALL FOR PAPERS
24th International Symposium on High Performance Interconnects
Huawei North America Headquarters
Santa Clara, California
August 24-26, 2016
Hot Interconnects is the premier international forum for researchers and
developers of state-of-the-art hardware and software architectures and
implementations for interconnection networks of all scales, ranging from
multi-core on-chip interconnects to those within systems, clusters,
datacenters, and clouds. This yearly conference is attended by leaders
in industry and academia. The atmosphere provides for a wealth of
opportunities to interact with individuals at the forefront of this
Themes include cross-cutting issues spanning computer systems,
networking technologies, and communication protocols for
high-performance interconnection networks. This conference is directed
particularly at new and exciting technology and product innovations in
these areas. Contributions should focus on real experimental systems,
prototypes, or leading-edge products and their performance evaluation.
Additional topics of interest are listed below.
This year's best papers on interconnect microarchitecture will be
invited to submit extended versions of their papers to a special edition
of IEEE Micro.
Building on last year's successful technical program, keynotes,
sessions, and panels on datacenter networking, requirements, and
solutions, in 2016 Hot Interconnects will be held at the Huawei North
America Headquarters in Santa Clara, CA. This year's conference focuses
on data-center, virtualized, and cloud networking. We hope you can join
* Paper abstract deadline: May 4, 2016 11:59PM AOE
* Paper submission deadline: May 11, 2016 11:59PM AOE
* Notification of acceptance: June 15, 2016
* Symposium: August 24-25, 2016
* Tutorials: August 26, 2016
An award will be given to the best student paper. To be eligible, at
least one of the paper's authors must be a full-time student at the time
of submission. In addition, HotI will provide student travel awards.
Information on travel awards can be found on our web site.
TOPICS OF INTEREST:
* Novel and innovative interconnect architectures
* Multi-core processor interconnects
* System-on-Chip Interconnects
* Advanced chip-to-chip communication technologies
* Optical interconnects
* Protocols and interfaces for inter-processor communication
* Survivability and fault-tolerance of interconnects
* High-speed packet processing engines and network processors
* System and storage area network architectures and protocols
* High-performance host-network interface architectures
* High-bandwidth and low-latency I/O
* Pb/s switching and routing technologies
* Innovative architectures for supporting collective communication
* Novel communication architectures to support cloud computing
* Centralized and distributed cloud interconnects
* Requirements driving high-performance interconnects
* Traffic characterization for HPC systems and commercial datacenters
* Software for Network/Fabric Bring-up, Configuration and Performance
Management, e.g., OpenFlow or OpenSM
* Data Center networking
We invite papers to be submitted either as regular, long papers (6-8
pages) or as short papers (3-4 pages). Short papers could be positional
papers, industry papers, or papers describing hot-off-the-press breaking
research results, and will judged accordingly and independently from the
* Accepted papers will be published in proceedings by the IEEE.
* Papers must contain sufficient technical detail to judge quality and
suitability for presentation.
* Submissions should include title, author, abstract, and be formatted
according to the two-column IEEE conference style guidelines.
* Long paper limit: 8 pages, single-spaced, 2 columns.
* Short paper limit: 4 pages, single-spaced, 2 columns.
* Papers should be submitted electronically through EasyChair at
* Paper title and abstract must be submitted by the abstract deadline.
* Full paper manuscript must be submitted by the paper deadline.
* Presentations are 30 minutes in a single-track conference format.
Ryan Grant, Sandia National Laboratories
Charlie Perkins, Huawei
TECHNICAL PROGRAM CHAIRS:
James Dinan, Intel
Ricki Williams, Oracle
TECHNICAL PROGRAM COMMITTEE:
Pavan Balaji, Argonne National Laboratory
Ron Brightwell, Sandia National Laboratories
Luca Carloni, Columbia University
Monia Ghobadi, Microsoft Research
Paolo Giaccone, Politecnico di Torino
Brice Goglin, INRIA
Mitch Gusat, IBM Zurich
Khaled Hamidouche, The Ohio State University
Dawei Huang, Oracle
Ajay Joshi, Boston University
Kirill Kogan, IMDEA Networks Institute
Tushar Krishna, Georgia Tech
Rami Melhem, University of Pittsburgh
Cyriel Minkenberg, IBM Zurich
Andrew Moore, University of Cambridge
Mondrian Nuessle, University of Heidelberg
Fabrizio Petrini, Intel Labs
Mohammad Javad Rashti, RNET Technologies
Galen Shipman, Los Alamos National Laboratory
Craig Stunkel, IBM TJ Watson
Keith Underwood, Intel
Eitan Zahavi, Mellanox