HLDVT: High Level Design Validation and Test

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Past:   Proceedings on DBLP

Future:  Post a CFP for 2018 or later   |   Invite the Organizers Email

 
 

All CFPs on WikiCFP

Event When Where Deadline
HLDVT 2017 19th IEEE International High-Level Design Validation and Test Workshop 2017
Oct 5, 2017 - Oct 6, 2017 Santa Cruz, CA Jul 23, 2017 (Jul 14, 2017)
HLDVT 2016 IEEE International High-Level Design Validation and Test Workshop
Oct 7, 2016 - Oct 8, 2016 Santa Cruz, CA, USA Jul 31, 2016 (Jul 17, 2016)
HLDVT 2012 IEEE International High-Level Design, Validation and Test Workshop
Nov 9, 2012 - Nov 10, 2012 Huntington Beach, California Jul 6, 2012 (Jun 29, 2012)
HLDVT 2011 IEEE International High Level Design Validation and Test Workshop
Nov 9, 2011 - Nov 11, 2011 Napa Valley, USA Jun 10, 2011
HLDVT 2010 IEEE International High Level Design Validation and Test Workshop
Jun 10, 2010 - Jun 12, 2010 Anaheim, USA Mar 7, 2010
 
 

Present CFP : 2017

The 19th HLDVT workshop aims to bring together a community of researchers in the areas of design validation and test of hardware, software, cyber-physical systems, smart-systems, biological systems, and bio-chips. The workshop addresses the integration of multiple functions on-chip/in-system at higher levels of design abstraction, and the techniques and methodologies for modeling, analyzing, and validating such systems. In particular, the workshop has become a unique forum for researchers and practitioners to discuss the practical issues associated with validation of extremely large designs in the application fields of: automotive, communication, green computing, healthcare and biological systems.

Topics of interest include, but are not limited to:

Simulation-Based Validation
Formal Verification, and Hybrid Methods
Design Abstraction, and Behavioral Modeling
Error Trace Interpretation, and Debugging
Functional safety/safety-critical system verification
On-Chip, and Core-Based Testing
Test Generation for Defects, Design Errors, and Delay Faults
Hardware/Software, and Mixed-Signal System Co-Validation
Emulation, and Prototyping
Post-silicon Validation, and Debug
Modeling, Simulation and Verification of Cyber-Physical Systems
Design and Test for AMS systems
Variability, Reliability and Dependability management of SoCs.

Paper Submission: The Program Committee invites authors to submit papers not to exceeding 8 pages (in the IEEE two-column conference format with 10-pt font size), describing original and unpublished work. Panels and special session proposals are also invited. All submissions must be made electronically in PDF format using the submission web site: https://easychair.org/conferences/?conf=hldvt17.
Paper Publication and Presenter Registration: All accepted papers will be made available on IEEE Xplore. The submission of a paper or panel proposal will be considered as evidence that upon acceptance, the author(s) will present their work. For the papers to appear in the program and proceedings, at least one different full workshop registration by an author is required before the submission of the camera-ready version. IEEE reserves the right to exclude a paper from distribution (e.g., removal from IEEE Xplore) if the paper is not presented at the workshop.
 

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