FPGA: Field Programmable Gate Arrays



Past:   Proceedings on DBLP

Future:  Post a CFP for 2024 or later   |   Invite the Organizers Email


All CFPs on WikiCFP

Event When Where Deadline
Feb 12, 2023 - Feb 14, 2023 Monterey Marriott Sep 23, 2022 (Sep 16, 2022)
FPGA 2016 Field Programmable Gate Arrays
Feb 21, 2016 - Feb 23, 2016 Monterey, California Sep 21, 2015
FPGA 2015 Field Programmable Gate Arrays
Feb 22, 2015 - Feb 24, 2015 Monterey, CA, USA Sep 22, 2014
FPGA 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Feb 26, 2014 - Feb 28, 2014 Monterey, CA Sep 20, 2013
FPGA 2013 ACM International Symposium on FPGAs
Feb 11, 2013 - Feb 13, 2013 Monterey, CA Sep 28, 2012
FPGA 2012 20th ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Feb 22, 2012 - Feb 24, 2012 Monterey, U.S.A. Sep 21, 2011
FPGA 2011 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Feb 27, 2011 - Mar 1, 2011 Monterey, CA Sep 20, 2010
FPGA 2010 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Feb 21, 2010 - Feb 23, 2010 Monterey, CA, USA Sep 20, 2009
FPGA 2009 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Feb 22, 2009 - Feb 24, 2009 Monterey, CA, USA Sep 28, 2008
FPGA 2008 ACM/SIGDA International Symposium on Field Programmable Gate Arrays
Feb 17, 2008 - Feb 19, 2008 Monterey, CA, USA Sep 16, 2007

Present CFP : 2023

Call for Papers – FPGA 2023
31st ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
The ACM/SIGDA International Symposium on Field-Programmable Gate Arrays is a premier conference for presentation of advances in FPGA technology. In 2023, the 31st edition of FPGA will be held in Monterey, California, USA. Accepted papers will be published in the conference proceedings and available in the ACM Digital Library. At least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel.

Submission website: Link will be available soon

Artifact evaluation guide: https://isfpga.org/artifact-evaluation/

Paper Submissions (with and without Artifacts)
We solicit research papers related to the following areas:

FPGA Architecture: Architectures for programmable logic fabrics or their components, including routing, flexible logic cells, embedded blocks (memory, DSP, processors), and I/O interfaces. Novel commercial architectures and architectural features.
FPGA Circuit Design: Circuits and layout techniques for the design of FPGAs. Impact of future process and design technologies on FPGAs as well as novel memory or nano-scale devices. Methods for analyzing and improving static and dynamic power consumption, power and clock distribution, yield, manufacturability, security, reliability, and testability.
CAD for FPGAs: Algorithms for synthesis, technology mapping, logic and timing optimization, clustering, placement, and routing of FPGAs. Novel design software for system-level partitioning, debug, and verification. Algorithms for modeling, analysis and optimization of timing and power.
High-Level Abstractions and Tools for FPGAs: General-purpose and domain-specific languages, tools, and techniques to facilitate the design, debugging and verification of FPGA-based applications and systems. Novel hardware/software co-design and high-level synthesis methodologies enabling digital signal processing, compute acceleration, networking, machine learning, and embedded systems.
FPGA-based and FPGA-like Computing Engines: Systems and software for compiled accelerators, reconfigurable/adaptive computing, and rapid-prototyping. Programmable overlay architectures implemented using FPGAs.
Applications and Design Studies: Implementation of novel designs on FPGAs establishing state-of-the-art in high-performance, low-power, security, or high-reliability. Designs leveraging unique capabilities of FPGA architectures or demonstrating significant improvements over alternative programmable technologies (e.g., CPU, GPU). Design studies or architecture explorations enabling improvement of FPGA architectures.
Research submissions can be in either of two categories:

Regular — at most 10 pages (excluding references), for a regular presentation at the conference.
Short — at most 6 pages (excluding references), for a brief presentation.
A paper submitted as either regular or short will only be considered in that category and may include artifacts if desired (see below for more details on artifact submission and evaluation).

Submission Process
Submissions of all types should be made in the form of an English language PDF file. Papers should use the sigconf ACM format template posted at http://www.acm.org/publications/proceedings-template/. LaTeX users should use the format used in the sample-sigconf.pdf file under the Samples folder of the zipped master file (available through the LaTeX (Version 1.84) link). Microsoft Word users can download the file Interim layout.docx under the Word Authors section of the page. Abstract and paper submissions in PDF must be received by 11:59 PM AoE (Anywhere-on-Earth time zone).

Submissions will be considered for acceptance as regular or short papers, workshop papers, or posters. Regular submissions related to the workshop topic may be scheduled for presentation during the workshop. Regular or workshop submissions will also be considered for acceptance as a poster. A paper submitted to the regular or short category will only be considered in that category. Once a paper has been submitted, its authorship list is considered to be fixed and final.

By submitting articles to an ACM Publication, authors are hereby acknowledging that they and their co-authors are subject to all ACM Publications Policies, including ACM’s new Publications Policy on Research Involving Human Participants and Subjects. Alleged violations of this policy or any ACM Publications Policy will be investigated by ACM and may result in a full retraction of their paper, in addition to other potential penalties, as per ACM Publications Policy.

Authors should ensure that they and their co-authors obtain an ORCID ID, so that they can complete the publishing process for accepted papers. ACM has been involved in ORCID from the start and ACM has recently made a commitment to collect ORCID IDs from all of their published authors. The collection process has started and will roll out as a requirement throughout 2022. ACM is committed to improve author discoverability, ensure proper attribution, and contribute to ongoing community efforts around name normalization; authors’ ORCID ID will help in these efforts.

Double Blind Policy
The FPGA Symposium uses a double-blind reviewing system. Manuscripts must not identify authors or their affiliations; those that do will not be considered. References to the authors’ prior work should be made in the 3rd person, in the same way one would reference work by others. If necessary to maintain anonymity, citations may be shown as “Removed for blind review,” but consider that this may impede a thorough review if the removed citation is crucial to understanding the submission. When necessary, authors should cite widely-available Open Source software website(s) without claiming ownership. Grant numbers and other government markings should also be blinded during the review process. Placing a preliminary version of the unpublished paper on arXiv is not disqualifying, but it is also not encouraged. Similarly, if a paper can be unblinded by active search, this is not considered to undermine the spirit of the double-blind review. However, there are resources to blind open-source repositories for review, including: https://github.com/tdurieux/anonymous_github.

If you have questions about how to meet these guidelines, please contact the program chair before the submission deadline.

Reviewer Conflict Policy
During paper submission, all author(s) conflicts must be registered with all possible program committee members. Conflicts are defined as all relationships that would prevent a reviewer from objectively evaluating the submitted work. This includes, but is not limited to, having within the past 5 years, 1) co-authored a publication, or 2) shared a funding award, and 3) shared at least one institutional affiliation. Note: if a conflict is left undeclared or a nonexistent conflict is declared in an attempt to manipulate the review process, the submission may be rejected.

For more information about the ACM Conflict of Interest Policy, see: https://www.acm.org/publications/policies/conflict-of-interest

Originality of Submissions
Papers submitted are guaranteed by the authors to be unique manuscripts and not previously published, currently accepted or under consideration for acceptance at another venue. They cannot be substantially similar to any other current/future conference, journal, or workshop submission(s) unless the content appeared at a venue that does not have archived proceedings.

Rebuttal Process
The conference review process includes a rebuttal phase for authors to provide an optional response to reviewers’ questions and comments. This information is considered during the final deliberation process.

Author participation
For inclusion in the ACM digital library, at least one of the authors of each accepted submission is required to present the work. Accommodations will be made for the authors who face travel restrictions or unforeseen difficulties with travel (more instruction will be available after the camera-ready submission).

Best Paper Award
Authors of this year’s best manuscripts will be eligible for the conference’s best paper awards. They will also be invited to extend their work for consideration in a special issue of ACM’s Transactions on Reconfigurable Technology and Systems (TRETS).

Artifact Evaluation
The conference will allow authors to submit accompanying artifacts for their paper submissions for evaluation. This process will allow ACM recognized badges to be associated with the final publication. The inclusion of artifacts with a submission is not required for a paper submission nor will any preference be given to submissions with artifacts over those without. Papers and artifacts will be subjected to separate and independent review processes. Artifact evaluation must NOT interfere with the double blind reviewing process of their accompanying papers, so all accompanying links in the paper to the artifacts should be blinded. All authors will be required at the time of paper submission to indicate if there will also be associated artifacts for evaluation. If artifacts will be included, a descriptor of their nature will be required.

For more information, see: https://isfpga.org/artifact-evaluation/

Diversity and Inclusion
The open exchange of ideas and the freedom of thought and expression are central to the aims and goals of the conference. The organizers aim and commit to providing a harassment-free accessible and pleasant conference experience with equity in rights for all. We want every participant to feel welcome, included and safe at the conference.

For more information, see: https://isfpga.org/statement-on-diversity-and-inclusion/

Important Dates
All submission deadlines are with respect to 11:59 pm Anywhere on Earth (UTC -12)

Abstracts Due (All Papers) September 16, 2022
(No Extensions)

Submissions Due (All Papers) September 23, 2022
(No Extensions)

Rebuttals Period October 24 – November 3, 2022
Notification of Acceptance (All Papers) Late November, 2022
Camera-Ready Submission Due Mid-December, 2022
Conference February 12 - February 14, 2023
Visa Application
Prospective authors and participants requiring a B-2 visa to enter the US should check the visa appointment wait time using this link: https://travel.state.gov/content/travel/en/us-visas.html and consider applying IMMEDIATELY for a visa, scheduling an appointment AFTER the 1st December 2022. By that date, notification of acceptance will have been sent out (if applicable), registrations will have been opened, and ACM will be able to deliver letters of support. To the best of our knowledge, the letter of support will never be required before the interview.

Organizing Committee:
General Chair Paolo Ienne EPFL
Program Chair Zhiru Zhang Cornell University
Publications Chair Jing (Jane) Li University of Pennsylvania
Finance Chair Michael Adler Intel
Publicity and Website Chair Dustin Richmond University of California, Santa Cruz
Artifact Evaluation Co-Chair Miriam Leeser Northeastern University
Artifact Evaluation Co-Chair Suhaib Fahmy
Artifact Evaluation Co-Chair Eli Bozorgzadeh
University of California, Irvine

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